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Receiver and semiconductor device

A technology for receiving circuits and switching circuits, applied in the field of receiving circuits, can solve the problems of input resistance degradation, interference wave suppression ratio degradation, and input resistance degradation resistance of filter circuits, and achieves improved convergence power, suppressed convergence power, and high rejection ratio. Effect

Inactive Publication Date: 2011-05-04
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the filter circuit has steep attenuation characteristics, regardless of whether the amplifier of the subsequent stage in the filter circuit is not saturated near the cutoff frequency, the amplifier of the preceding stage in the filter circuit is saturated, and the input resistance characteristic of the entire filter circuit is deteriorated.
[0014] When the frequency band where the input resistant characteristic deteriorates overlaps with the band of the interference wave close to the desired wave, the interference wave suppression ratio deteriorates.

Method used

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  • Receiver and semiconductor device
  • Receiver and semiconductor device
  • Receiver and semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0051] figure 1 It is an overall block diagram of the receiving circuit 100 according to Embodiment 1 of the present invention. The receiving circuit 100 includes: an AGC loop 10 for amplifying a received signal input from an input terminal IN to a constant power; a frequency converter 40 for converting the received signal amplified by the AGC loop 10 into an intermediate frequency; The active filter of the signal of the desired frequency is the filter bank 20 of the intermediate frequency low-pass filter IFLPF; it is used to detect the power difference between the intermediate node and the output node of the filter bank, and control the convergence power of the AGC loop 10 A power difference detection unit 30 .

[0052] The AGC loop 10 has two reference voltages, Vref1 and Vref2, as reference voltages. The reference voltage Vref1 is a frequency near the cutoff frequency of the intermediate frequency low pass filter IFLPF, and is used to suppress the convergence power of th...

Embodiment 2

[0066] Figure 11 A block diagram of a receiving circuit 100A of Embodiment 2 is shown in . exist Figure 11 In the description, the structure and function are the same as figure 1 The receiving circuit 100 is substantially the same module composed with the figure 1 The same reference numerals are used, and detailed explanations are omitted. In the receiving circuit 100A of the second embodiment, an AD converter ADC1 and a digital filter DF are provided in the subsequent stage of the intermediate frequency low-pass filter IFLPF. In Embodiment 2, a filter bank 20A is constituted by an intermediate frequency low-pass filter IFLPF which is an active filter, and a digital filter DF provided in a subsequent stage. In Embodiment 2, the digital filter DF, the output node power detector DET3, and the voltage difference detection unit 31A are constituted by digital circuits.

[0067] The basic operation of the second embodiment is the same as that of the first embodiment. When ...

Embodiment 3

[0072] Figure 12 It is a block diagram of the receiving circuit 100B of the third embodiment. In Example 3, from Figure 11 In the second embodiment shown, the connection is changed in such a way that the intermediate node power detection unit DET2 is configured by a digital circuit and detects the electric power of the intermediate node of the digital filter DF. In this case, compared with the first and second embodiments, the attenuation characteristic of the intermediate frequency low-pass filter IFLPF can be set more smoothly. Since the attenuation characteristics of the intermediate frequency low-pass filter IFLPF are gentle, although the desired wave is attenuated to a certain extent, the interference wave 1 also appears in the output of the intermediate frequency low-pass filter IFLPF. The information of interference wave 1 remains in the input node of DF. Thus, by detecting the level of the intermediate node and the output node of the digital filter DF by the inter...

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PUM

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Abstract

A receiving circuit and a semiconductor device, can obtain a high restraining rate of an interference wave, even when an interference wave that has a frequency near that of a desired wave to be received is received or an interference wave that has a frequency away from that of the desired wave to be received is received. The receiving circuit includes an automatic gain control (AGC) loop and a filter group that is arranged downstream of the AGC loop. The filter group includes an active filter. The receiver further includes a power difference detector and a switch circuit. The power difference detector detects a power difference between intermediate and output nodes of the filter group to detect presence of an interference wave that is different from a desired wave and that has a frequency near that of the desired wave. The switch circuit switches an operation to suppress a convergence power of the AGC loop when the power difference detector detects the interference wave.

Description

technical field [0001] The present invention relates to a receiving circuit and a semiconductor device in which the receiving circuit is formed on a semiconductor substrate. In particular, it relates to receiving circuits with AGC loops and active filters. Background technique [0002] A receiving circuit of a superheterodyne system that converts a received signal into an intermediate frequency signal and performs signal processing on the received signal converted into an intermediate frequency (Intermediate Frequency, hereinafter referred to as IF) is widely used. A mixer circuit is used for conversion of the intermediate frequency, and the frequency difference between the local oscillator (Local Oscillator, LO) signal input to the mixer circuit and the received signal is equal to the frequency difference of the intermediate frequency signal (IF signal: output signal of the mixer circuit). frequency. [0003] Here, when the frequency of the IF signal is assumed to be cons...

Claims

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Application Information

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IPC IPC(8): H04B1/10H04B1/16
CPCH03G1/0088H03G3/3052H04B1/10
Inventor 浦川辰也松野典朗
Owner RENESAS ELECTRONICS CORP