Thyristor for electrostatic discharge

Abstract

The invention discloses a thyristor for electrostatic discharge which comprises a parasitic PNP tube, a parasitic NPN tube and a short-channel MOS (metal oxide semiconductor) tube; an emitter electrode of the parasitic PNP tube is connected with a positive terminal, the base electrode of the parasitic PNP tube is connected with the positive terminal through a parasitic resistance of an N-well; acollector electrode of the parasitic PNP tube is connected with the base electrode, and is connected with a negative terminal through a parasitic resistance of a P-well; an emitter electrode of the parasitic PNP tube is connected with the negative terminal, a collector electrode of the parasitic NPN tube is connected with the positive terminal through a parasitic resistance of the N-well; and theside walls at the two sides of the short-channel MOS tube grid electrode respectively extend to an N <+> doping region which is the boundary region of the N-well and the P-well and a P<+> doping region adjacent to the N <+> region. In the invention, through reducing the grid length of the MOS tube, when the ESD (electrostatic discharge) voltage is lower, the thyristor can be conducted, and the trigger voltage of the thyristor is reduced further.

Description

technical field [0001] The invention relates to the field of protection circuit design of semiconductor integrated circuits, in particular to a thyristor used for electrostatic discharge. Background technique [0002] During the manufacture, packaging and use of integrated circuit chips, ESD (Electro Static Discharge, electrostatic discharge) phenomenon will occur. ESD is manifested as an instantaneous high-voltage pulse, and the large amount of charge released in this instant is very likely to destroy the functional devices inside the integrated circuit. Therefore, a thyristor for electrostatic discharge is usually provided between the internal circuit and the external signal source or power supply. [0003] At present, the structure of a typical low trigger voltage discharge unit thyristor in a commonly used electrostatic protection circuit is as follows: figure 1 As shown, in which, an N well and a P well are arranged on a P-type substrate, and an N well is formed by io...

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Problems solved by technology

[0005] However, the research of the inventors found that the trigger voltage of the thyristor with the above structure is still too high in some occasions, for example, the breakdown voltage of the gate oxide layer for a 3.3V device is 10V, while the trigger voltage of the thyristor with the above structure is as high as 8.5 Above V, and for 3.3V devices, the trigger voltage that can meet the false triggering requirements is 5.5V. It can be seen that the thyristor with the above structure is prone to false triggering

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