ESD (electrostatic discharge) protection circuit

Abstract

The invention provides an ESD (electrostatic discharge) protection circuit which comprises a first power wire, a second power wire, a virtual power wire, a first input / output pad, a functional unit, a first discharge unit, a second discharge unit, and a first hold-off diode, wherein the first end of the functional unit is coupled with the first input / output pad, the second end is coupled with the first power wire, and the third end is coupled with the second power wire; the first end of the first discharge unit is coupled with the first input / output pad and the first end of the functional unit, and the second end is coupled with the virtual power wire; the first end of the second discharge unit is coupled with the first input / output pad and the first end of the functional unit, and the second end is coupled with the second power wire; and the anode of the first hold-off diode is coupled with the virtual power wire, and the cathode is coupled with the first power wire. Through the invention, the performance of the ESD protection circuit is improved.

Description

technical field [0001] The invention relates to an electrostatic discharge (ESD) circuit, in particular to an ESD protection circuit. Background technique [0002] Integrated circuits are prone to destructive electrostatic discharge (ESD) during manufacturing, assembly, testing, or final application, so that integrated circuits are damaged by static electricity. Therefore, usually in an integrated circuit, an ESD protection circuit is usually formed, so that the input / output pad (I / O pad) is coupled with a discharge unit that can discharge static electricity on the I / O pad, so that the I / O The static electricity on the pad is released to reduce the damage caused by static electricity to the integrated circuit. For example, an electrostatic discharge (ESD) protection circuit is disclosed in the patent document with the application number "01807873.7". In addition, there are also a large number of ESD protection circuits in the prior art, and an existing ESD protection circu...

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Problems solved by technology

For example, the second device may be in the working state, so the I / O pad2 of the second device may be high level; while the first device is in the non-working state, which includes two cases: the first case is the first power supply of the first device The line VDD is grounded, so that when the I / O pad2 of the second device is at a high level, there will be a large leakage current from the I / O pad2 of the second device through the I / O pad1-first-two of the first device. Transistor D1 flows to the first power line VDD; in the second case, the first power line VDD of the first device is empty, so that when the I / O pad2 of the second device is high, the I / O of the first device pad1-the first diode D1, the first power line VDD of the first device is also controlled to a high level, so that the internal circuit of one device may malfunction due to being powered on

[0006] In addition, there are four commonly used ESD protection circuits: PS (pad force positive pulse, VSS grounded), NS (pad force negative pulse, VS S grounded), PD (pad force positive pulse, VDD grounded) or ND (pad force negative pulse , VDDgrounded) The problem of poor electrostatic protection ability in the working mode

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