Method for fabricating a gate dielectric layer

Abstract

A method for fabricating a gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer. The silicon oxide is prevented from being generated on the surface of the top of the substrate to keep the performance characteristics of the device.

Description

technical field [0001] The present invention relates to integrated circuit fabrication, and more particularly to a semiconductor device having a gate dielectric layer. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in successive generations of IC production, each with smaller and more complex circuits than the previous generation. As the size of transistors shrinks, the thickness of the gate dielectric layer must be thinned as the gate channel length is reduced to maintain performance. However, in order to reduce the gate leakage current, it is necessary to use a high-k gate dielectric layer as the gate dielectric layer used in future advanced nodes, which can have a thicker physical thickness while maintaining the same equivalent thickness. [0003] Figure 1A and Figure 1B Cross-sectional views of the high-k gate dielectric layer 112 of a conv...

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Problems solved by technology

[0005] However, the problem faced by the above method is that, if too many oxygen radicals penetrate the high-k gate dielectric layer 112 and reach the top surface of the substrate 102, undesired silicon oxide will be formed on the substrate 102. top surface, thus increasing the equivalent thickness of the high-k gate dielectric layer 112

As a result, device performance characteristics, such as threshold voltage, are reduced

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