Flip-chip bonding method and flip-chip bonding construction of non-array bumps
A bonding method and bump technology, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problem of inconsistent filling speed of primer, save the filling time and amount of primer, and solve the problem of gas filling. well problem, avoiding the effect of chip tilt
Active Publication Date: 2011-11-09
WALTON ADVANCED ENG INC
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Problems solved by technology
[0006] The main purpose of the present invention is to overcome the defects of the existing flip-chip bonding method and structure, and provide a new flip-chip bonding method and structure of non-array bumps. The technical problem to be solved is to avoid The chip tilt of the non-array bump can better solve the air pocket problem caused by the inconsistent filling speed of the underfill in the flip-chip bonding process of the non-array bump, which is very suitable for practical use.
Method used
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no. 1 Embodiment
[0075] According to the first embodiment of the present invention, a non-array bump flip-chip bonding method is exemplified in figure 2 The block flow diagram for Figure 3A to Figure 3G Cross-sectional views of components in each step. The non-array bump flip-chip bonding method is based on figure 2 , including the following main steps: step 1 of "providing a substrate", step 2 of "forming the support colloid on the upper surface of the substrate", step 3 of "bonding the chip to the substrate", step 4 of "pressing the chip" and Step 5 of "Providing Underfill", the components shown on each step refer to Figure 3A to Figure 3G , detailed below.
[0076] First, go to step 1. see Figure 3A As shown, a substrate 210 is provided, the upper surface 211 of which is provided with a plurality of pads 212 . In detail, the pads 212 can be arranged in single or double rows on the central area of the upper surface 211 to provide electrical connection. The main body of the subs...
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The invention relates to a flip-chip bonding method and a flip-chip bonding construction of non-array bumps. The method comprises the following steps of: providing a substrate; forming a plurality of supporting colloids on an upper surface of the substrate, and forming a primer channel between the adjacent supporting colloids; carrying out flip-chip bonding on a chip to the substrate to make a bump blank area of an active surface of the chip adhered to the supporting colloids; pressing the chip to form a material extrusion frame, which exceeds the chip, on the supporting colloids and bond a plurality of non-array bumps to a bonding pad of the substrate in the primer channel, wherein the material extrusion frame has a plurality of openings which are communicated with the primer channel; and providing a bottom filling adhesive through one of the openings until the primer channel is filled with the bottom filling adhesive for sealing the bumps. Therefore, the air trap problem caused by inconsistency of the conventional comprehensive primer filling speed can be solved, and the filling time and using quantity of the primer can be saved.
Description
technical field [0001] The invention relates to a packaging and manufacturing technology of a semiconductor device, in particular to a flip-chip bonding method and structure of non-array bumps. Background technique [0002] In the packaging process of semiconductor chips, the integrated circuit chip must be connected with a chip carrier such as a substrate or a lead frame to perform the function of electronic signal transmission. Conventional methods for electrically connecting a chip to a chip carrier include wire bonding, tape automated bonding (TAB) and flip chip bonding. Among them, flip-chip bonding can shorten the transmission distance between the chip and the substrate, and has better electrical performance than wire bonding, so it is gradually popularized. Chips currently used in the flip-chip bonding process have bumps arranged in an array, and the bumps are evenly dispersed on the active surface of the chip by using a reconfiguration circuit layer. Recently, some...
Claims
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IPC IPC(8): H01L21/50H01L21/60H01L21/56H01L23/485H01L23/28
CPCH01L24/83H01L2224/83192H01L2224/73204H01L2924/14H01L2924/15787H01L2924/00
Inventor 李国源陈永祥
Owner WALTON ADVANCED ENG INC