A high sustaining voltage n-type electrostatic protection semiconductor device

Abstract

A high sustaining voltage N-type electrostatic protection semiconductor device, comprising: a semiconductor substrate, on which a buried oxide layer is arranged, above which is an N-type doped semiconductor drift region, and a P well region is arranged on Above the N-type doped semiconductor drift region, while the field oxide layer, metal layer, gate oxide layer, polysilicon gate and oxide layer are arranged on the upper surface of the device, and the N-type source region and the P-type contact region are arranged in the P well , characterized in that: a P-type doped semiconductor region is also provided in the P well, and the P-type doped semiconductor region is located under the N-type source region and the gate oxide layer. The device can effectively increase the holding voltage during electrostatic protection, so the device has better anti-latch-up ability.

Description

technical field [0001] The invention relates to the field of reliability of power semiconductor devices, and more specifically relates to a new structure of a high sustaining voltage semiconductor transistor suitable for electrostatic protection. Background technique [0002] With the increasing demand for energy saving, the performance of power integrated circuit products has attracted more and more attention, and the reliability of the circuit has also attracted more and more attention from circuit design engineers. Electrostatic discharge is a very important reliability issue, and it is also one of the main causes of failure of many electronic products. With the continuous reduction of process feature size, electronic products are more vulnerable to electrostatic discharge damage, so the problem of electrostatic protection has become increasingly serious. [0003] At present, in the problem of electrostatic protection, it is generally on the input and output ports of the...

AI Technical Summary

Problems solved by technology

The development of N-type lateral double-diffused metal-oxide-semiconductor transistor and its structure in the low-voltage process of electrostatic protection has become mature, but there are big problems in the design of electrostatic protection in the high-voltage process

The main problem is that the maintenance voltage of the N-type lateral double-diffused metal-oxide semiconductor transistor is too low, and there is a great risk of latch-up, which makes the design of the electrostatic protection of the N-type lateral double-diffused metal-oxide semiconductor transistor in the high-voltage process and applications are greatly limited

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