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Production method of shallow trench isolation

A fabrication method and shallow trench technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as stress, lattice structure mismatch, peeling, etc., to improve morphology, reduce stress, reduce The effect of small thickness

Inactive Publication Date: 2012-02-15
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, since the nitride layer does not match the lattice structure of the silicon wafer, an excessively thick nitride layer will cause serious stress problems and even cause peeling

Method used

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  • Production method of shallow trench isolation
  • Production method of shallow trench isolation
  • Production method of shallow trench isolation

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Embodiment Construction

[0034] The present invention will be described in further detail below in conjunction with accompanying drawing:

[0035] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0036] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of ...

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Abstract

The invention relates to a production method of a shallow trench isolation, comprising the following steps of: sequentially depositing a pad oxidation layer, a pad nitridation layer, an oxide hard mould and a nitride hard mould on a silicon sheet; forming a shallow trench which penetrates through the structure on the silicon sheet and partial silicon sheet; corroding the nitride hard mould, the oxide hard mould and the pad nitridation layer; depositing an oxidization film on the surface of the structure; and filling insulating medium into the shallow trench so as to form an insulating medium layer, and chemically and mechanically grinding the layer to form a shallow trench isolation structure. According to the production method provided by the invention, the nitride hard mould is used as a hard mask for etching the shallow trench isolation; the oxide hard mould is used as a stress releasing layer of the nitride hard mould and a sacrificial layer for corroding the pad nitridation layer; therefore, the initial thickness of the pad nitridation layer is reduced and the stress is decreased; and furthermore, the thickness of the pad oxidation layer is reduced and the shape of a shallow trench isolation pit is improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for manufacturing shallow trench isolation. Background technique [0002] In the deep submicron integrated circuit process, shallow trench isolation (STI, shallow trench isolation) is a process for making isolation regions between transistor active regions on the substrate. Due to its ability to provide smaller isolation dimensions, flat Due to the advantages of an ultra-thin surface, it gradually replaced the local field oxidation process and became the mainstream isolation process. [0003] In the shallow trench isolation process, the nitride layer is usually used as a hard mask for etching and chemical mechanical polishing (CMP). And, its residual thickness is the starting point of shallow trench isolation step height (STI overhang) adjustment after chemical mechanical polishing. In the shallow trench isolation process, the nitride layer will be consumed by multi-step ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
Inventor 曹永峰
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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