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Clamp circuit and flash electro-erasable memory

A clamping circuit, write memory technology, applied in static memory, read-only memory, information storage and other directions, can solve problems such as disadvantage, complicated circuit, simplified process, etc., to achieve stable operation, reduce temperature effect, reduce consumption effect Effect

Active Publication Date: 2012-03-21
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this kind of circuit is relatively complicated, which is not conducive to simplifying the process

Method used

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  • Clamp circuit and flash electro-erasable memory
  • Clamp circuit and flash electro-erasable memory
  • Clamp circuit and flash electro-erasable memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0032] figure 1 Shown is a schematic structural diagram of an existing flash electric erasable memory circuit, and the output voltage of the charge pump is not less than the clamping voltage of the clamping circuit. When the charge pump outputs a voltage to the clamping circuit, an electric field will be generated at both ends of the clamping circuit. Under the action of the electric field, the first diode is turned on, the second diode is broken down, and the output voltage of the clamping circuit It is equal to the breakdown voltage of the second diode, but the breakdown voltage of the second diode is seriously affected by temperature, and cannot provide a safe and stable working voltage for the memory array within the working temperature range.

[0033] The inventors of the present invention have found that under the action of an electric field, electrons in the second diode migrate from the p region to the barrier region, and holes migrate from the n region to the p region...

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Abstract

The invention relates to a clamp circuit which comprises a diode and a control device; the control device is composed of a gate-grounded NMOS transistor (GGNMOS). Thereinto, a substrate is grounded; a source electrode, a drain electrode and a cathode of the diode are electrically connected; an anode of the diode is connected to an external power supply. By using the control device composed of a gate-grounded NMOS transistor (GGNMOS), the clamp circuit of the invention generates GGNMOS GIDL breakdown formed by both avalanche breakdown and zener breakdown under the action of external voltage, thus effectively improves the temperature coefficient of the clamp circuit, and reduces the consumption effect of the clamp circuit. Correspondingly, the invention also relates to a flash electro-erasable memory which adopts the novel clamp circuit; compared with existing flash electro-erasable memories, the flash electro-erasable memory provided by the invention has significantly improved temperature effect, and improved working voltage stability within a temperature range of -40-125 DEG C.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a clamping circuit capable of improving the temperature effect of a flash electric erasable memory and its corresponding flash electric erasable memory. Background technique [0002] In the power supply circuit of the current flash electric erasable memory (Flash EEPROM), the voltage provided by the charge pump (V cp ) are used for writing and erasing memory cells. The operating temperature range of Flash EEPROM is -40~125°C. Within the operating temperature range of -40~125°C, the safe working voltage of the storage unit is 15.5~16.5V. If the actual working voltage exceeds the safe working voltage range, it will cause memory The NMOS transistor in the cell is broken down or the write operation is insufficient, so V cp The stability of the device is critical to the performance of the device. However, the current situation is that the output voltage characteristic of the charge pump is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/14
Inventor 谷炜炜杨震郭兵金凤吉詹奕鹏
Owner SEMICON MFG INT (SHANGHAI) CORP
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