MIM (metal-insulation-metal) capacitor

Abstract

The invention discloses an MIM (metal-insulation-metal) capacitor which comprises a substrate, a metal shielding layer, a first metal layer, a first isolation layer, an insulation medium layer and a second metal layer, wherein the metal shielding layer is formed on the surface of the substrate; the first metal layer is formed on the metal shielding layer; the first isolation layer is formed by surrounding the first metal layer; the insulation medium layer is formed on the first metal layer; the second metal layer is formed on the insulation medium layer; and the second metal layer is connected with the isolation medium layer through a contact hole. Through the capacitor provided by the invention, the mutual influence between unit capacitors less is extremely small and the parasitic capacitance is reduced fully, thus the influence of the parasitic capacitance on ADC (analog to digital converter) performance is reduced.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a MIM capacitor in the field of semiconductors. Background technique [0002] Capacitors are passive components commonly used in VLSI, which mainly include polysilicon-insulator-polysilicon (PIP, Polysilicon-Insulator-Polysilicon), metal-insulator-silicon (MIS, Metal-Insulator-Silicon) and metal-insulator - Metals (MIM, Metal-Insulator-Metal), etc. Among them, because MIM capacitors have the least interference on transistors and can provide better linearity (Linearity) and symmetry (Symmetry), they have been more widely used, especially in mixed-signal (Mixed-signal) and radio frequency ( RF, Radio Frequency) field. [0003] figure 1 It is a schematic cross-sectional structure diagram of an existing MIM capacitor, referring to figure 1 , the structure of the MIM capacitor 100 mainly includes: a metal shielding layer 101; a lower plate layer 102 formed on the metal shielding laye...

AI Technical Summary

Problems solved by technology

[0004] For this capacitor 100, the capacitance Ca is the required capacitance for design, yet, the capacitor 100 also has the following parasitic capacitances: CFm is the fringe capacitance from the edge of the upper plate to the lower plate, and CFct is the capacitance from the edge of the insulating medium to the lower plate The fringe capacitance, the parasitic capacitance CF=CFm+CFct will affect the accuracy of the calculation of the capacitance Ca; CPm is the fringe capacitance from the edge of the upper plate to the ground (metal shielding layer or grounded chip substrate), and CPct is the edge to ground of the insulating medium ( The fringe capacitance of the metal shielding layer or grounded chip substrate), the parasitic capacitance CP=CPm+CPct will affect the performance of the ADC (Analog-to-Digital Converter, analog-to-digital converter) using this capacitor

[0005] In summary, it can be seen that the MIM capacitors of the prior art have the problem that the accuracy of the capacitance value calculation and the performance of the analog-to-digital converter using the capacitor are affected by the presence of parasitic capacitance. Therefore, it is necessary to propose improved technical means to solve the problem. this question

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