The application discloses a hierarchical background calibration method for a time-interleaved ADC (
Analog to Digital Converter), which is suitable for a multi-channel time-interleaved and single-channel two-stage ADC structure analog-
digital conversion system. After
code conversion and data alignment of each sub-channel output code
stream, the method firstly estimates and eliminates each channel misadjustment and mismatch by using a second-order digital
tracking loop after down-sampling, then constructs a
gain error iterative update loop based on channel output power consistency to obtain a digital
gain compensation coefficient, and finally performs same-frequency
quadrature demodulation on each channel sequence after misadjustment and
gain correction, extracts each channel phase information and converts it into a relative sampling
time sequence deviation, and quantitatively compensates through a programmable
clock delay unit. The method classifies static mismatch and dynamic
time sequence mismatch, can suppress
interleaving spur without interrupting normal sampling, improves the SNDR (
Signal-to-
Noise and
Distortion Ratio) and SFDR (
Spurious Free Dynamic Range) of the time-interleaved ADC, is simple in hardware implementation, is suitable for RTL (
Register Transfer Level) implementation and on-
chip background operation.