Image sensor package structure of micro salient point interconnection structure and realization method of image sensor package structure

Abstract

The invention relates to an image sensor package structure of a micro salient point interconnection structure and a realization method of the image sensor package structure. The image sensor package structure comprises a chip body (1), an isolation layer (6), a silicon groove (13) and an opening (2-1), wherein the chip body (1) is provided with a chip internal passivation layer (2), a chip internal metal layer (3) and a photosensitive area (4); metal micro salient points (7) are formed in the opening (2-1) and on the lower surface of the chip internal passivation layer (2); insulating layers (8) are selectively arranged on the lower surface of the chip body, in the silicon groove, the exposed lower surface of the chip internal passivation layer and the surfaces of the metal micro salient points; the insulating layers are provided with openings to form blind holes (8-1); metal circuit layers (9) are filled in the blind holes (8-1) and are selectively formed on the surfaces of the insulating layers (8); circuit protecting layers (10) are selectively arranged on the insulating layers (8) and the metal circuit layers (9); and welded balls (11) are arranged at the parts of the metal circuit layers (9), at which the circuit protecting layers (10) are exposed. The image sensor package structure disclosed by the invention has the advantages of simple structure, small process difficulty and favorable interconnection reliability.

Description

technical field [0001] The invention relates to a wafer-level image sensor packaging structure and an implementation method, and belongs to the technical field of semiconductor packaging. Background technique [0002] An image sensor is a semiconductor device that converts external light signals into electrical signals, and the obtained electrical signals are processed for final imaging. Wafer-level image sensor packaging is a new type of image sensor packaging. Compared with traditional lead-bonded packaging, it has the advantages of small package size, low price, and the photosensitive area is not easy to be polluted during downstream assembly. It is receiving more and more attention. focus on. Since the chip electrodes of the image sensor or the internal metal layer of the chip and the photosensitive area of ​​the chip are located on the front of the chip, wafer-level packaging needs to reserve the front of the chip as a photosensitive window, and redistribute the intern...

AI Technical Summary

Problems solved by technology

Due to the introduction of through-silicon via interconnection in this wafer-level image sensor packaging method, the packaging structure is complicated; and the through-silicon via interconnection technology is not yet mature, often due to poor insulation in the hole, incomplete interconnection windows, and incomplete metal filling. Leading to failure or poor reliability, this kind of wafer-level image sensor packaging using TSV interconnection has the problems of high process difficulty and low interconnection reliability

[0004] Among them, Tessera in the United States, Samsung in South Korea, Toshiba in Japan, and STMicroelectronics all adopt the packaging form of through-silicon via interconnection structure, but the packaging process must be realized with chip design. Design collaboration is very difficult. Although Tessera's patented technology solves some problems in terms of packaging factories not relying on chip design, there are still many defects in the ease of implementation of the process and the reliability of the structure.

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