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Vertical dual-diffusion metal oxide semiconductor (VDMOS) device with back surface embedded into strain medium region, and manufacturing method for VDMOS device

A dielectric region and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as the inability to reduce the resistance of the drift region, avoid latch-up effects, avoid high-temperature processes, and reduce on-resistance. Effect

Inactive Publication Date: 2012-04-18
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method can only reduce the channel resistance and the resistance of the JFET region, and cannot reduce the resistance of the drift region

Method used

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  • Vertical dual-diffusion metal oxide semiconductor (VDMOS) device with back surface embedded into strain medium region, and manufacturing method for VDMOS device
  • Vertical dual-diffusion metal oxide semiconductor (VDMOS) device with back surface embedded into strain medium region, and manufacturing method for VDMOS device
  • Vertical dual-diffusion metal oxide semiconductor (VDMOS) device with back surface embedded into strain medium region, and manufacturing method for VDMOS device

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Embodiment Construction

[0026] The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, only used to explain the present invention, and should not be construed as a limitation of the present invention.

[0027] In the description of the present invention, it should be understood that the terms "portrait", "horizontal", "upper", "lower", "front", "rear", "left", "right", "vertical", The orientations or positional relationships indicated by "horizontal", "top", "bottom", "inside", "outside", etc. are based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description...

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Abstract

The invention provides a vertical dual-diffusion metal oxide semiconductor (VDMOS) device with a back surface embedded into a strain medium region and a manufacturing method for the VDMOS device. The VDMOS device comprises a drain region, a drift region, a junction field-effect transistor (JFET) region, a channel region, a source region, a medium, a grid, an isolation medium, source metal and a strain medium region. By the VDMOS device, a trench is trenched on the back and a strain film is embedded into the trench, so that stress is introduced into the whole current path of the VDMOS device, and the carrier mobility on a current transmission path is improved; therefore, conduction resistance of the VDMOS device can be reduced, and a latch-up effect in the VDMOS device is avoided. By the manufacturing method, the strain is introduced into a semiconductor by a method for covering an insulating strain layer, a necessary high temperature process of an epitaxial technology is avoided, a surface structure of the device is not needed to be changed at all, and the device can be directly applied to design of existing devices.

Description

technical field [0001] The invention relates to the technical field of semiconductor design and manufacture, in particular to a VDMOSFET (vertical double diffusion Metal-Oxide-Semiconductor field effect transistor, vertical double diffusion metal oxide semiconductor field effect transistor) device with backside embedded strained dielectric region and a preparation method thereof . Background technique [0002] VDMOS device is a transistor widely used in the field of power electronics technology, and it is used in switching power supplies as a switching device in many cases. As a power electronic device, one of its most important indicators is the on-resistance. For a VDMOS device, according to its device structure, the on-resistance is generally composed of contact resistance, source resistance, channel resistance, JFET (Junction field effect transistor, The junction field effect transistor) region resistance, drift region resistance and drain region resistance are composed...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/10H01L21/336
CPCH01L29/7843H01L29/7802H01L29/7849H01L29/0653H01L29/1095H01L29/66712
Inventor 万欣周伟松梁仁荣刘道广许军
Owner TSINGHUA UNIV