Test structure for semiconductor chip and method for measuring dielectric characteristic

Abstract

The present invention discloses a test structure for a semiconductor chip, and a method for measuring dielectric characteristic. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer. The test structure can accurately know the time of cracking and can obtain the cracking phenomenon before the packaging of the semiconductor chip.

Description

technical field [0001] The invention relates to a test structure of a semiconductor chip and a method for measuring characteristics using the structure, in particular to a test structure for measuring the electrical characteristics of a low-permittivity dielectric in a semiconductor chip and a method for measuring characteristics using the structure. Background technique [0002] The semiconductor integrated circuit industry is booming, and the technological evolution of integrated circuit materials has created the generation of integrated circuits. The new generation of integrated circuits has smaller volumes and more complex circuit architectures. However, these advances also significantly increase the complexity of the integrated circuit manufacturing process. Therefore, in order to realize the miniaturization of integrated circuits, the development of integrated circuit manufacturing technology is also an inevitable trend. On the way to the evolution of integrated circu...

AI Technical Summary

Problems solved by technology

However, due to the size reduction of integrated circuits and internal components, existing mechanical and electrical characteristic measurements must be performed after the packaging of integrated circuits is completed

In this way, it takes a lot of detection time and additional resources, resulting in a cost burden

[0004] Therefore, although the existing methods for measuring low-permittivity dielectrics can obtain their due efficacy, they cannot achieve satisfactory efficiency in all aspects.

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