Metal interconnecting method

Abstract

The invention provides a metal interconnecting method which is characterized in that: after silicon nitride and a second interlayer dielectric are sequentially deposited on a first interlayer dielectric with a first metal layer, the silicon nitride is adopted as an etching stopping layer, the second interlayer dielectric is primarily etched to form a through hole, and the method comprises the following steps that: a bottom reflection resistant coat is coated in the through hole and on the second interlayer dielectric, and a low-temperature silicon oxide layer is deposited in the through hole and on the second interlayer dielectric; the low-temperature silicon oxide layer and the second interlayer dielectric are secondarily etched by adopting a second photoetched pattern after being photoetched as a mask, a polymer side wall is formed on the side wall of the through hole, while a groove is formed in the second interlayer dielectric, the polymer side wall is removed through a third-time etching, so the polymer side wall can be prevented from dropping on the surface of the first metal layer during the subsequent process of the cineration removal of the photoetched pattern and over-etching removal of the remained silicon nitride layer, the favorable contact between metal copper inside the through hole and an interface of the first metal layer can be guaranteed during the subsequent metal copper filling step, and the failure rate of the semiconductor device caused by the open circuit can be reduced.

Description

technical field [0001] The invention relates to a semiconductor manufacturing method, in particular to a metal interconnection method. Background technique [0002] With the progress of the semiconductor manufacturing process, the area of ​​the semiconductor chip is getting smaller and smaller, and at the same time, the size and the number of semiconductor devices integrated on the same semiconductor chip are getting smaller and smaller. The semiconductor devices form a semiconductor circuit through metal interconnections to realize signal transmission between the semiconductor devices. Metal interconnects are composed of high-density metal lines and interlayer dielectrics between the metal lines. The resistance capacitance delay phenomenon (Resistance Capacitance Delay, RC Delay) of the metal interconnection reduces the signal transmission rate of the semiconductor circuit, thereby reducing the working speed of the semiconductor device. [0003] The signal transmission ra...

AI Technical Summary

Problems solved by technology

[0025] In view of this, the technical problem solved by the present invention is: in the process of etching metal interconnection lines with low dielectric constant materials as interlayer dielectrics, the polymer sidewalls generated by dry etching will be in subsequent ashing and lining. During the pad removal step, it falls to the bottom of the via hole, causing poor contact or even an open circuit at the interface between the metal copper filled in the via hole and the first metal layer below it, resulting in failure of the semiconductor device

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