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MOSFET (Metal Oxide Semiconductor Field Effect Transistor) gate membrane structure compatible with self-aligned hole and pattern manufacturing method

A self-alignment and film structure technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as inability to produce, cannot meet the requirements of large driving current for surface channels, and achieve the effect of avoiding peeling

Inactive Publication Date: 2012-05-09
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, when the two are combined, there will be special requirements for the gate film structure: simply using traditional doped polysilicon-silicon nitride cannot meet the large driving current requirements required by the surface channel, and metal silicide is used. If silicon nitride is used as the gate film, it cannot be used in production because the high temperature process in the process will cause peeling of the silicon nitride layer on the surface.
Therefore, the current technical bottleneck lies in the film structure of the gate

Method used

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  • MOSFET (Metal Oxide Semiconductor Field Effect Transistor) gate membrane structure compatible with self-aligned hole and pattern manufacturing method
  • MOSFET (Metal Oxide Semiconductor Field Effect Transistor) gate membrane structure compatible with self-aligned hole and pattern manufacturing method
  • MOSFET (Metal Oxide Semiconductor Field Effect Transistor) gate membrane structure compatible with self-aligned hole and pattern manufacturing method

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Embodiment Construction

[0021] Such as Figure 5 As shown, the present invention proposes a novel MOSFET gate film structure, the following thin film structures are deposited sequentially on the silicon substrate, namely gate oxide film, gate polysilicon, metal silicide (usually tungsten silicide), Silicon oxide on the pad layer and silicon nitride for self-aligned through holes. This series of films constitutes the MOSFET gate film layer as a whole, that is, the final pattern vertical structure of the gate layer.

[0022] Among them, the gate polysilicon layer is deposited by low-pressure chemical vapor deposition, N-type saturated doping in the NMOS region (P well substrate), and P-type saturated doping in the PMOS region (N well substrate), so that both MOS can form surface channels. Figure 5 is the finally formed gate section structure (including side walls);

[0023] The metal silicide layer is deposited by physical vapor phase, and its thickness can be changed according to the resistance req...

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Abstract

The invention discloses an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) gate membrane structure compatible with a self-aligned hole and a pattern manufacturing method. The MOSFET gate membrane structure includes the following thin film structures on a silicon substrate from bottom to top: gate silicon oxide, gate polycrystalline silicon, gate metal silicide, pad silicon oxide and top silicon nitride. By using the gate membrane layer structure provided by the invention, gate polycrystalline silicon is doped at different regions respectively so as to guarantee surface channels of different types of MOS transistors; the structure of the metal silicide can meet adequately large driving current; the pad oxide film buffers stress between the silicon nitride membrane and the metal silicide required by a self-aligned hole process, and peeling of the silicon nitride membrane in a subsequent high-temperature process is avoided.

Description

technical field [0001] The invention relates to an integrated circuit production and manufacturing method, in particular to a MOSFET gate film structure and its pattern manufacturing technology. Background technique [0002] With the increasing integration of devices in semiconductor integrated circuit chips, the size of commonly used metal-oxide-semiconductor field effect transistors (MOSFETs) will be further reduced, and a larger driving current is required in the working state. In order to reduce the size of the device and save the surface space of the wafer, the industry often adopts the so-called "self-aligned via" (SAC) method; and to increase the drive current, especially the MOS transistor of the P-type channel, it is necessary to use the surface Channel (surface channel) devices. However, when the two are combined, there will be special requirements for the gate film structure: simply using traditional doped polysilicon-silicon nitride cannot meet the large driving...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/423H01L21/285
Inventor 陈瑜孙尧罗啸
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP