Satellite reception control signal detection circuit
A technology for controlling signals and detecting circuits. It is used in the measurement of electrical variables, current/voltage, and television. It can solve the problems of low reliability and a large number of components, and achieve the effect of reducing the total number of components.
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Embodiment 1
[0017] Embodiment one: if figure 1 As shown, it is the first embodiment of a satellite receiving control signal detection circuit provided by the present invention, which is a chip U1 with at least VDD pins, VSS pins, and ZENER pins. The internal circuit includes a comparator COMP1, base and The transistor PNP1 connected to the negative terminal of the comparator COMP1, the positive terminal connected to the emitter of the transistor PNP1 and the first current source i1 connected to the negative terminal of the comparator COMP1, the positive terminal connected to the negative terminal of the comparator COMP1 The second current source i2 connected with the negative terminal connected to the collector of the transistor PNP1. The peripheral circuit includes a voltage regulator circuit located between the VDD pin and the VSS pin, and a voltage regulator tube Z1 connected to the ZENER pin. The positive end of the first current source i1 is connected to the VDD pin at the same time...
Embodiment 2
[0020] Embodiment two: if figure 2 As shown, it is a second embodiment of a satellite receiving control signal detection circuit combined with a current source circuit provided by the present invention, which is roughly similar in structure to the first embodiment, and it is a chip with at least VDD pins, VSS pins, and ZENER pins U1, the internal circuit includes a comparator COMP1, a transistor PNP1 whose base is connected to the reverse terminal of the comparator COMP1, a current source composed of the second resistor R2 and the first PMOS transistor P1, and the first PMOS transistor P1 connected in parallel Two, three PMOS transistors P2, P3, and a current mirror composed of the first NMOS transistor N1 and the second NMOS transistor N2. The collector of the triode PNP1 is connected to the VSS pin, and the ZENER pin is connected to the first resistor R1 and the voltage regulator tube Z1.
[0021] The electrical signal VCC sent from the receiver is input from the VDD pin, ...
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