Safety scanning register, safety scan chain and scanning method of safety scan chain

Abstract

The invention discloses a safety scanning register, a safety scan chain and a scanning method of the safety scan chain and belongs to the field of measurability design of an integrated circuit. The safety scanning register consists of a D trigger, an XOR gate and an alternative multiplexer. A data input end of the D trigger is connected with an output end of the alternative multiplexer. An output end of the D trigger is connected with a first input end of the XOR gate. A second input end of the XOR gate is connected with a second data input end of the alternative multiplexer. The safety scan chain disclosed by the invention comprises conventional scanning registers and the safety scanning registers. All the registers are cascaded. The number and the positions of the registers are determined according to a certain rule. The safety scan chain disclosed by the invention can resist the reset attack. Sufficient safety can be obtained by small area cost. The safety scan chain has high practicality.

Description

technical field [0001] The invention belongs to the field of integrated circuit testability design, and relates to a scanning register, a scanning chain and a scanning method for safety testing. Background technique [0002] As the most widely used design for test (Design for Test) structure in VLSI (Very Large Scale Integration) design, the scan chain enhances the controllability and observability of the chip and provides Good testability. Usually, in the design process of a semiconductor chip, it is not only necessary to design a functional circuit to realize a predetermined function, but also to design a scan test circuit (scan chain) for testing a chip manufacturing defect. [0003] Traditional scan registers such as figure 1 As shown, its ports include: data terminal input (D terminal), used to receive function input signals; scan input terminal (SI terminal), used to receive scan input signals; scan enable terminal (SE terminal), used to receive enable Enable signal...

AI Technical Summary

Problems solved by technology

[0010] The first type is to remove the registers storing security information from the scan chain, so that unauthorized users cannot obtain the security information in the registers through the scan chain, but this type of scheme reduces the testability of the chip and increases Chip testing cost and difficulty

[0011] The second category is to restrict the chip from switching between the function mode and the test mode arbitrarily, so that the attacker cannot use the scan chain to detect the internal register status of the chip, but this kind of scheme increases the area greatly, and due to changing the normal working mode The path cannot provide an At-Speed ​​Test. More importantly, the security of this method depends on one or two key control signals. An attacker only needs to destroy these key signal lines to pass through the scan chain. Access registers that store security information

[0012] The third category is to add a combined unit in the scan path, and perform hardware encryption on the test pattern of the scan chain, so that unauthorized users cannot use the controllability of the scan chain to set the scan register, nor can they use the observability of the scan chain. The state of the sex detection scan register

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