Trapped charge capture type flash memory array structure and operation method thereof

Abstract

The invention provides a trapped charge capture type flash memory array structure, which comprises a substrate and a two-dimension memory array structure formed on the substrate, wherein the two-dimension memory array structure comprises a plurality of storage unit arrays in parallel arrangement in the first direction, a plurality of character lines in parallel arrangement in the second direction, a source line in the second direction and a plurality of position lines in parallel arrangement in the first direction, each storage unit array comprises a plurality of storage units, each storage unit is a silicon-oxidation layer-silicon nitride-oxidation layer-silicon type (SONOS) memory, and the adjacent storage units are mutually isolated; the character lines are connected with a grid electrode layer of the storage units; the source line connects the source ends of all storage units; and the position lines are connected with drain ends of the storage units. The array structure is applied to independent NOR FLASH, a peripheral circuit can be simplified, the erasing speed can be accelerated, the embedded NOR FLASH is adopted, the electricity leakage and reading error problems caused by erasing can be avoided, the circuit power consumption is reduced, and simultaneously, the storage density is improved.

Description

technical field

[0001] The invention relates to the technical field of non-volatile memory, in particular to a charge-trapping flash memory array structure and an operation method thereof. Background technique

[0002] Flash (FLASH) memory has the characteristic that the stored data will not be lost after power failure, and is especially suitable for fields such as mobile communication and computer storage components.

[0003] The traditional NOR FLASH array is a single-tube parallel architecture, such as figure 1 shown. Erase is performed in units of blocks. Affected by various factors such as process and operating conditions, the erasing operation will cause a certain proportion of cells to be over-erased, and the threshold voltage of the over-erased cells is negative, that is, over-erased. like figure 1 As shown, when unit A is read, if unit B is over-erased, its threshold voltage is negative, and leakage will occur, so that the current on the bit line BL1 is shared b...

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