High-speed parallel interface circuit

Abstract

The invention is suitable for a digital communication field and provides a high-speed parallel interface circuit. The circuit comprises: a LVDS receiving module, a sampling conversion module, a bit synchronization module and a word synchronization module, wherein the LVDS receiving module receives data and carries out shaping; the sampling conversion module is connected with the LVDS receiving module, samples the data output by the LVDS receiving module and converts into the parallel data under a sampling clock; the bit synchronization module is connected with the sampling conversion module, provides the sampling clock for the sampling conversion module and adjusts the sampling clock to an optimum sampling point according to the data output by the sampling conversion module; the word synchronization module is connected with the bit synchronization module and carries out shift adjustment to the data output by the bit synchronization module. According to the invention, a pure digital sampling clock phase adjustment and word adjustment mode used to accurately sample and recover source synchronization data. Through a multiplexer which calculates, feeds back and outputs training data sampling clock phase to the sampling clock, the phase of the sampling clock can be changed so that the clock sampling generates at a center of a data effective window.

Description

technical field [0001] The invention belongs to the field of digital communication, in particular to a high-speed parallel interface circuit. Background technique [0002] With the vigorous development of digital communication services, the communication system poses higher challenges to the transmission bandwidth. For example, the 10Gbps high-speed parallel interface has a wide range of applications in optical fiber communication, data exchange, and network communication. One of the bottlenecks of high-speed parallel transmission is the effective recovery of data. There are two main problems in data recovery: First, when the single-line transmission rate becomes faster and faster, the time window occupied by each bit of data continues to decrease, resulting in It is difficult for the clock to sample accurately in the effective window of the data; second, due to the different delays of the data paths transmitted in parallel, the receiving end cannot effectively receive the p...

AI Technical Summary

Problems solved by technology

One of the bottlenecks of high-speed parallel transmission is the effective recovery of data. There are two main problems in data recovery: First, when the single-line transmission rate becomes faster and faster, the time window occupied by each bit of data continues to decrease, resulting in It is difficult for the clock to sample accurately in the effective window of the data; second, due to the different delays of the data paths transmitted in parallel, the receiving end cannot effectively receive the parallel transmitted data synchronously

The clock data recovery circuit is mainly composed of an edge detector, a frequency capturer, a phase tracker and a clock restorer. First, the edge detector detects the jump of the data edge to extract the phase information, and then adjusts the phase of the clock through the self-oscillation of the phase extraction circuit. , and finally through the clock recovery device to monitor and adjust the clock frequency output by the phase extraction circuit. Analog circuits with extremely high precision requirements also have special requirements for the production process of integrated circuits, and the large phase jitter of the clock data recovery circuit for sudden data signals may easily cause the phase-locked loop to lose lock, and the locking time of the phase-locked loop is relatively long. Long, often can not meet the fast synchronization requirements

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