Scheduling method of network-on-chip router based on network information

Abstract

The invention discloses a scheduling method of a network-on-chip router based on network information, and mainly solves the problem that the router has limited buffer space and longer grouping time so as to seriously block a network. The scheduling method is finished through two stages as follows: at the first stage, an input arbitration unit selects an input queue as a response queue according to the three parameters, namely hop count from a source node to a destination node, the hop count from a current node to the destination node and lock virtual channel number of a local input port; and at the second stage, an output arbitration unit selects according to the three parameters, namely, the lock virtual channel number of an output link, the hop count from the source node to the destination node and the hop count from the current node to the destination node, and a best transmission path is selected between an input port and an output port grouped on the network-on-chip router through the scheduling of two stages. The scheduling method provided by the invention has the advantages of low time delay, high throughput and balanced grouping link flow, and can optimize distribution of an inner path of the network-on-chip router.

Description

technical field [0001] The invention belongs to the field of network technology, and relates to a scheduling method for a system-level chip and an on-chip network router, which is suitable for low-blocking and fast communication of on-chip network services of different scales in the router. Background technique [0002] The system-on-chip (SoC) based on the bus architecture uses intellectual property IP core multiplexing technology to design integrated circuits. These IP cores are usually general-purpose processors, digital signal processors DSP, microprocessors ARM, memory modules RAM, etc. With the development of semiconductor technology and the rapid increase of chip processor frequency, more and more IP cores are integrated on a single silicon chip, and the SoC bus architecture faces many problems, mainly in three aspects: (1) address space problem. Since only one pair of nodes is allowed to communicate at the same time, when the number of communications increases, the a...

AI Technical Summary

Problems solved by technology

Since only one pair of nodes is allowed to communicate at the same time, when the number of communications increases, the address space is limited and cannot support the interconnection between more IP cores, which limits the scalability of the system

(2) Long interconnection problem

(3) Power consumption problem

However, this kind of router has serious head-of-line blocking, so the throughput of the network is not high, and the queue waiting delay caused by head-of-line blocking is also relatively long.

In order to alleviate the head-of-line blocking problem, researchers proposed a virtual channel router structure, which uses time-division multiplexing to share links and bandwidth, which not only alleviates the head-of-line blocking problem but also improves network performance. This kind of virtual channel router shares the cache unit by setting a virtual channel for each port. Each virtual channel has an exclusive first-in-first-out queue. However, due to the limitation of chip area and power consumption, the queue length of each port is limited. The length of the stored business packet is also very limited, so when the packet length is long and the business load of the network is heavy, the micro-slices of a packet may be blocked in

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