Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

ldmos device and its manufacturing method

A device manufacturing method and epitaxial layer technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as process defects and unclean silicon dioxide grinding, and achieve the effect of reducing process defects

Active Publication Date: 2015-09-09
CSMC TECH FAB2 CO LTD
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During the subsequent chemical mechanical polishing (CMP), due to the existence of the high steps, the silicon dioxide near the drift region is not cleaned, resulting in process defects

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • ldmos device and its manufacturing method
  • ldmos device and its manufacturing method
  • ldmos device and its manufacturing method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0041] As mentioned in the background technology section, in the manufacturing process of LDMOS devices, the LOCOS process is often used to form a field oxide layer above the drift region, and the field oxide layer is generally used as an isolation layer for devices in the active region (mostly high-voltage devices). However, the field oxide layer formed by the LOCOS process is difficult to apply to the process of 0.18 μm and below 0.18 μm due to the limitation of the “bird’s beak” effect; and after the field oxide layer is formed above the drift region, the field oxide layer About half of the thickness of the substrate is higher than the surface of the substrate, so a step is formed. The existence of the step prevents the subsequent CMP process from planarizing the substrate, resulting in process defects.

[0042] Based on this, the present invention provides a kind of LDMOS device manufacturing method, with reference to figure 1 , the method specifically includes the followi...

Embodiment 2

[0055] The LDMOS device manufacturing method provided by the present invention is described in detail below with a specific embodiment, refer to figure 2 , the method specifically includes the following steps:

[0056] Step S11: providing a substrate, the substrate includes a body layer, an epitaxial layer, and a deep well region in the epitaxial layer.

[0057] The "in the epitaxial layer" mentioned in this embodiment refers to a region extending downward from the surface of the epitaxial layer to a certain depth, which belongs to a part of the epitaxial layer; the "on the epitaxial layer" refers to the region upward from the surface of the epitaxial layer , this region does not belong to the epitaxial layer itself, and the meanings expressed in other descriptions can also be deduced by analogy.

[0058] refer to image 3 , the figure shows a body layer 100 , an epitaxial layer 101 on the body layer 100 and a deep well region 102 in the epitaxial layer 101 .

[0059] In t...

Embodiment 3

[0087] The present invention also provides a kind of LDMOS device, refer to Figure 8 , the LDMOS device includes: a base, the base includes a body layer 100, an epitaxial layer 101, and a deep well region 102 located in the epitaxial layer 101; a first shallow trench dielectric layer 108 located in the deep well region 102 and The second shallow trench dielectric layer 109 .

[0088] The depths of the first shallow trench dielectric layer 108 and the second shallow trench dielectric layer 109 are both 100nm, and the sidewalls of the first shallow trench dielectric layer 108 and the second shallow trench dielectric layer 109 and the epitaxial The angle between the surface of the layer 101 is 80°-90°.

[0089] The formation process of the first shallow trench dielectric layer 108 and the second shallow trench dielectric layer 109 in the embodiment of the present invention is as follows: first, an isolation dielectric layer, a hard mask layer and an anti-reflection layer are se...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method of fabricating a LDMOS device includesproviding a substrate having a body layer, an epitaxial layer overlying the body layer, and a deep well region disposed in a middle portion of the epitaxial layer, forming an isolation dielectric layer on the deep well region and forming a hard mask layer on the isolation dielectric layer, forming a shallow trench in the deep well region by a mask having a drift region pattern, and forming a shallow trench dielectric layer in the shallow trench. The method further includes forming a deep trench at an edge of the deep well region, filling the deep trench with a dielectric material, and planarizing the filled deep trench and the shallow trench dielectric layer. The method also includes forming a groove above the drift region, and filling a dielectric layer in the groove.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, and more specifically, relates to an LDMOS device and a manufacturing method thereof. Background technique [0002] With the continuous development of semiconductor technology, LDMOS (Lateral Double-diffuse MOS) devices are widely used in mobile phones due to their good short channel characteristics, especially in 900MHz in cellular phones. With the continuous growth of the mobile communication market (especially the cellular communication market), the manufacturing process of LDMOS devices is becoming more and more mature. [0003] In a conventional process, the formation process of an LDMOS device includes: forming a drift region and an active region on a substrate. Wherein, the local oxidation of silicon (LOCOS) process is generally used to form a field oxide layer as an isolation layer above the drift region, which specifically includes the following steps: [0004] 1. ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/762H01L29/78H01L29/06
CPCH01L29/0653H01L29/7835H01L29/66659H01L21/76224H01L29/0847
Inventor 韩广涛孙贵鹏林峰马春霞黄枫
Owner CSMC TECH FAB2 CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com