Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package

A chip stacking and production method technology, applied in the direction of electrical components, semiconductor devices, electrical solid devices, etc., can solve problems such as poor insulation performance, affecting chip heat dissipation, and affecting the height of bonding wires connecting IC chips and carrier pads, etc. , to achieve the effect of facilitating heat dissipation, improving insulation performance and solving height problems

Active Publication Date: 2014-06-25
TIANSHUI HUATIAN TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] At present, stacked packaging is to directly stack and bond IC chips through adhesive sheets, which affects the height of the bonding wire connecting the IC chip and the carrier pad, and the insulation performance between adjacent chips is not good, which also affects the heat dissipation of the chip.

Method used

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  • Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package
  • Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0104] The chip thickness is reduced from the original wafer thickness to the final thickness of 100μm; the rough grinding range is from the original wafer thickness to 150μm + film thickness, and the rough grinding speed is 2μm / s; the fine grinding thickness ranges from 150μm + film thickness to 100μm + Film thickness, fine grinding speed 0.6μm / s, chip warping prevention process is used during wafer thinning; the roughness of thinned wafer is 0.10mm, using DISC 3350 dicing machine to dicing, using anti-fragmentation , Anti-crack dicing process software control technology, dicing feed speed ≤10mm / s; get separated IC chip with bandage ring; thin the single wafer to make the final thickness 110μm; during the thinning process of single wafer, rough grinding Range from the original thickness of single wafer to 160μm + film thickness, rough grinding speed 3μm / s; fine grinding thickness range from 160μm + film thickness to 110μm + film thickness, fine grinding speed 15μm / s; core is a...

Embodiment 2

[0106] The chip thickness is reduced from the original wafer thickness to the final thickness of 100μm; the rough grinding range is from the original wafer thickness to 150μm + film thickness, and the rough grinding speed is 5μm / s; the fine grinding thickness ranges from 150μm + film thickness to 100μm +Adhesive film thickness, fine grinding speed 0.3μm / s, chip warping prevention process is used during wafer thinning; the roughness of the thinned wafer is 0.05mm; double knife dicing machine is used for dicing, and anti- Chip and anti-crack scribing process software control technology, scribing feed speed ≤10mm / s; get separated IC chip with bandage ring. Thin the single wafer to a final thickness of 120μm; during the process of single wafer thinning, the rough grinding range is from the original thickness of the single wafer to 170μm + film thickness, and the rough grinding speed is 5μm / s; the fine grinding thickness ranges from 170μm + film thickness To 120μm + film thickness, ...

Embodiment 3

[0108] The chip thickness is reduced from the original wafer thickness to the final thickness of 100μm; the rough grinding range is from the original wafer thickness to 150μm + film thickness, and the rough grinding speed is 3.5μm / s; the fine grinding thickness ranges from 150μm + film thickness to 100μm + film thickness, fine grinding speed 0.45μm / s, chip warping prevention process is used in the process of wafer thinning; the roughness of the thinned wafer is 0.08mm, using A-WD-3000TXB dicing machine Chips; using anti-fragment and anti-crack dicing technology software control technology, dicing feed speed ≤10mm / s; get separated IC chip with bandage ring; thin the single chip to make the final thickness of 100μm; single chip thinning In the process, the rough grinding range is from the original thickness of the single wafer to 150μm + film thickness, and the rough grinding speed is 4μm / s; the fine grinding thickness ranges from 150μm + film thickness to 100μm + film thickness, ...

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Abstract

The invention discloses a multilayer spacer type IC (Integrated Circuit) chip stacked package of a substrate and a production method of the package. The package comprises a BT (Bismaleimide Triazine) substrate, wherein at least two IC chips are bonded onto a carrier of the BT substrate, all the IC chips are stacked and bonded in sequence, a bonding pad on each IC chip is connected with a bonding pad on the BT substrate through a bonding wire, a plastic package body is fixedly packaged on the BT substrate, and a spacer is bonded between every two adjacent IC chips. The production method comprises the steps of: thinning and scribing wafers and the spacers, bonding the IC chips onto the carrier of the BT substrate, then bonding the spacers onto the IC chips, and bonding the IC chips onto the spacers again to make the stacking layer number meet a use requirement, wherein the processes of baking, plasma cleaning and pressure welding are needed once each IC chip is bonded; and then bonding the IC chips continuously, and performing subsequent procedures by adopting the prior art to prepare the multilayer spacer type IC chip stacked package of the substrate with the required layer number. According to the package disclosed by the invention, the height of the bonding wire is not influenced, and the heat radiation and insulation performances of the chips are improved.

Description

technical field [0001] The invention belongs to the technical field of electronic information automation components manufacturing, and relates to an IC chip integrated circuit package, in particular to a substrate multi-layer spacer type IC chip stack package, and the invention also relates to a package of the stack package production method. Background technique [0002] With the expansion of the market demand for smaller, lighter and more efficient mobile phones and the growth of electronic devices for handheld computers (PADs), the research and development of electronic packaging technology is promoted to be more miniaturized and more functional. It is an important technical means for products to be smaller, lighter and more functional, and has been increasingly valued by customers of packaging companies. Various mobile phone digital cameras, various smart cards and portable instruments are the application fields of stacked packaging products. The multifunctional technol...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L23/488H01L23/31H01L21/60H01L21/56
CPCH01L2224/48227H01L2924/15311H01L2924/181H01L2224/32145H01L2224/45144H01L2224/45147H01L2224/73265H01L2924/00014H01L2924/00012H01L2924/00
Inventor 郭小伟朱文辉慕蔚王永忠
Owner TIANSHUI HUATIAN TECH
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