Silicon-controlled rectifier device embedded with Zener trigger structure

Abstract

The invention discloses a silicon-controlled rectifier device embedded with a Zener trigger structure, which comprises a P- substrate layer, wherein an N- well and a P- well which are connected side by side are arranged on the P- substrate layer, and a junction between the N- well and the P- well is provided with a third N+ active injection region; a first N+ active injection region and a first P+ active injection region are arranged on the N- well side by side; a second P+ active injection region and a second N+ active injection region are arranged on the P- well side by side; the first N+ active injection region and the first P+ active injection region are connected through a first metal electrode; and the second P+ active injection region and the second N+ active injection region are connected through a second metal electrode. According to the silicon-controlled rectifier device embedded with the Zener trigger structure, a Zener diode is used as an auxiliary triggering unit, the trigger voltage of a silicon-controlled rectifier can be further effectively reduced, the ESD (Electro Static Discharge) protection of low trigger voltage is realized, and thus the silicon-controlled rectifier can be directly applied to ESD protection of a deep sub-micron integrated circuit chip with a power supply domain of 1.2-5V.

Description

technical field [0001] The invention belongs to the technical field of electrostatic protection for integrated circuits, and in particular relates to a thyristor device embedded with a Zener trigger structure. Background technique [0002] With the rapid development of electronic information technology, the current semiconductor devices tend to be miniaturized, high-density and multi-functional, especially for applications such as fashion consumer electronics and portable products that have strict requirements on the motherboard area, they are vulnerable to electrostatic discharge (ESD) )Impact. Static electricity exists all the time and everywhere. In the 1960s, with the emergence of MOS devices that are very sensitive to static electricity, the problem of static electricity also appeared. In the 1970s, the problem of static electricity became more and more serious. The density of the circuit is getting bigger and bigger. On the one hand, the thickness of the silicon dioxi...

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Problems solved by technology

figure 1 Among them, VDD represents the operating voltage of the integrated circuit power supply, and BVox represents the voltage limit that the internal devices of the integrated circuit can withstand. The area between VDD and BVox is called the ESD design window, and the failure current It2 can be used to measure the robustness of the ESD device. During the ESD design process, the trigger voltage Vt1 and the sustain voltage Vh must be controlled within the ESD design window, such as figure 1 As shown in A, if the current-voltage characteristic curve (IV curve) of the ESD device exceeds BVox, such as figure 1 The Vt1 shown in B, that is, Vt1 exceeds the voltage limit of the protected circuit, and the internal circuit will be burned. If the current-voltage characteristic curve (IV curve) of the ESD device is lower than VDD, such as figure 1 The Vh shown in C, that is, Vh is lower than the power supply voltage for the normal operation of the integrated circuit, a latch-up effect will occur, affecting the normal operation of the circuit

[0009] In the current field of ESD protection, such as figure 2 The silicon controlled rectifier device shown has attracted important attention due to its strong robustness per unit area, but the trigger voltage of the silicon controlled rectifier device is too high in the hysteresis effect, so it is difficult to be directly applied to chip protection. Lowering the trigger voltage is still under exploration

[0010] image 3 It is an improved structure aimed at the problem that the trigger voltage of the traditional thyristor structure is too high. The main method is to add a layer of N+ or P+ active injection region on the boundary of the original N-well and P-well. The silicon-controlled structure has played a certain role in reducing the trigger voltage, but it still cannot meet the ESD protection requirements of integrated circuits.

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