Method for preparing double-stress thin film

Abstract

The invention relates to the field of semiconductor manufacture, in particular to a method for preparing a double-stress thin film. The method for preparing the double-stress thin film is used for preparing a high-stress double-stress thin film by replacing a traditional silicon nitride thin film with a nitride-doped silicon carbide thin film. The method for preparing the double-stress thin film can not only meet the requirements of RC (resistance capacitance) delay of a plurality of advanced devices, but also avoid the problem of existence of an overlapping area in the traditional silicon nitride double-stress thin film process, thereby solving the loss of yield caused by the overlapping area; and the method for preparing the double-stress thin film is simple and easy to implement.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a method for preparing a double stress film. Background technique [0002] Nowadays, the strained silicon technology (Stain silicon) integration process has been widely used at the 45nm node, especially for the pre-metal dielectric deposition process (Pre-Metal Dielectric, referred to as PMD), dual stress film (Dual Stress Liner, DSL for short) has become mandatory to increase the speed of the device. [0003] However, at present, the industry generally chooses silicon nitride film as the double stress film. Since the dielectric constant of silicon nitride film is relatively high (k is generally around 7.0), it will cause a certain time delay (RC delay), that is, it cannot meet some advanced requirements. The device's requirement for time delay (RC delay) causes the device speed to fail to meet the process requirements. [0004] In the current inte...

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Problems solved by technology

[0003]However, at present, the industry generally chooses silicon nitride film as the double stress film. Since the dielectric constant of silicon nitride film is relatively high (k is generally around 7.0), it will It causes a certain time delay (RC delay), that is, it cannot meet the requirements of some advanced devices for time delay (RC delay), and the speed of the device cannot meet the process requirements.

[0004]In the current integration process, for the problem of overlap of different stress films, it is mainly adjusted by using dry etching process or considered in layout design to try to Reduce the impact on yield, but increase the difficulty of process control

[0005]Figure 1 is a schematic diagram of the flow structure of the sputtering process used in the background technology of the present invention to improve the problem of overlapping regions of different stress films; such as Figure 1, IMEC proposes a sputtering method to improve the overlapping area of ​​different stress films. On the semiconductor structure, after the sputtering process (Sputter), deposit the interlayer dielectric layer (Inter Layer Dielectric, referred to as ILD), and use the chemical mechanical polishing process (Chemical Mechanical Polishing, referred to as CMP) for planarization treatment, and then etch back Forming CA holes, although it can solve the problem of overlapping films with different stresses, there is an obvious risk of plasma damage (plasma damage)

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