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Control circuit, transistor control system and method, and device

A technology for controlling transistors and control circuits, applied in transistors, semiconductor devices, circuits, etc., can solve problems such as the upper limit of the channel length, the gate is not fully insulated, and the IC is difficult to drive GaN-HEMT, etc., to reduce power consumption, The effect of the acceleration switch

Inactive Publication Date: 2015-12-16
TRANSPHORM JAPAN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in order to be driven by a driving voltage of about 10V generated by an IC (Integrated Circuit), the insulating layer between the gate and the channel of GaN-HEMT is configured to be thin
Therefore, the gate of the GaN-HEMT is not sufficiently insulated
Also, there is an upper limit to the channel length of GaN-HEMTs because large gate capacitance makes it difficult for ICs to drive GaN-HEMTs

Method used

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  • Control circuit, transistor control system and method, and device
  • Control circuit, transistor control system and method, and device
  • Control circuit, transistor control system and method, and device

Examples

Experimental program
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Effect test

no. 1 Embodiment

[0028] (1) Structure

[0029] figure 1 is a configuration diagram of the control device (circuit) 2 according to the present embodiment. exist figure 1 In , the transistor 4 controlled by the control device 2 and the load inductor 6 of the transistor 4 are shown together with the control device 2 . The load inductor 6 is, for example, an element included in a power supply system. figure 2 is a cross-sectional view of transistor 4.

[0030] Such as figure 2 As shown, the transistor 4 is a GaN-HEMT formed on a Si substrate 8 . This GaN-HEMT includes an AlGaN / GaN heterostructure 12 , a source electrode (hereinafter referred to as source) 14 , a drain electrode (hereinafter referred to as drain) 16 , a gate 18 and FP20 .

[0031] AlGaN / GaN heterostructure 12 includes undoped GaN layer 22 and AlGaN barrier layer 24 . Piezoelectric polarization occurs due to the lattice distortion that occurs between the AlGaN barrier layer 24 and the GaN layer 22 . Due to this piezoelectr...

no. 2 Embodiment

[0088] Figure 13 It is a configuration diagram of a PFC (power factor control) circuit 76 including a control system 74 of the present embodiment. Such as Figure 13 As shown, the PFC circuit 76 of this embodiment includes a control system 74 , an excitation circuit 78 and a feedback circuit 80 .

[0089] The control system 74 includes the control circuit 2 and the transistor 4 . In the first embodiment described above, the control circuit 2 and the transistor 4 have been described. The excitation circuit 78 includes an inductor 82 , a diode 84 and a capacitor 86 . The feedback circuit 80 includes a first resistor R1 and a second resistor R2.

[0090] The input power is connected to the input terminal Vin of the drive circuit 78 . Constant voltage power supply, AC power supply, rectified power supply that generates rectified voltage, etc. can be provided as input power supply. For example, the voltage of the input power source is 100V. The excitation circuit 78 charges...

no. 3 Embodiment

[0096] This embodiment relates to a control system including a transistor different from that of the second embodiment. Figure 14 is a cross-sectional view of the transistor 4a in the control system of this embodiment. Figure 15 It is the equivalent circuit of transistor 4a. Such as Figure 14 As shown, the transistor 4a includes a first FP20a and a second FP20b.

[0097] Therefore, the equivalent circuit of transistor 4a (see Figure 15 ) includes a GaN-HEMT 30, a first FP transistor 32a, and a second FP transistor 32b. The GaN-HEMT 30, the first FP transistor 32a, and the second FP transistor 32b correspond to the gate 18, the first FP20a, and the second FP20b, respectively.

[0098] The gate drive pulse generated by the control circuit 2 is supplied to the gate 18 . Also, the FP driving pulse generated by the control circuit 2 is supplied to the first FP 20a. On the other hand, the source S of the transistor 4a is connected to the second FP20b (see Figure 15 ).

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Abstract

A control circuit, a transistor control system and method, and a device, wherein the control circuit is used to control a transistor including a gate and a field plate, and the control circuit includes: a detection circuit for detecting a driving timing used to drive the transistor; a timing control circuit for controlling a first driving timing for driving the gate and a second driving timing for driving the field plate in response to the driving timing; and a driving circuit for controlling in response to the The gate is driven with a first driving sequence, and the field plate is driven in response to the second driving sequence. By adopting the control circuit and method provided by the invention, the power consumption of the transistor can be reduced, and the switching of the transistor can be accelerated.

Description

technical field [0001] Embodiments discussed herein relate to a control circuit for a transistor, a control system for a transistor, and a method for controlling a transistor. Background technique [0002] GaN-HEMT (High Electron Mobility Transistor) having GaN with high electrical breakdown field strength and high mobility HEMT is promising as a high power switching element. However, in order to be driven by a driving voltage of about 10 V generated by an IC (Integrated Circuit), the insulating layer between the gate and the channel of the GaN-HEMT is configured to be thin. Therefore, the gate of the GaN-HEMT is not sufficiently insulated. Also, there is an upper limit to the channel length of GaN-HEMTs because large gate capacitance makes it difficult for ICs to drive GaN-HEMTs. As a result, the source-to-drain breakdown voltage of the GaN-HEMT does not exceed about 100V. [0003] Therefore, a GaN-HEMT provided with a field plate (hereinafter referred to as "FP") in ord...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K17/04
CPCH03K17/08122
Inventor 竹前义博
Owner TRANSPHORM JAPAN