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Array substrate manufacturing method, array substrate and display device

A manufacturing method and an array substrate technology, which are applied in semiconductor/solid-state device manufacturing, optics, instruments, etc., can solve the problems of doping structure offset, high processing cost, and long processing time, so as to reduce Ioff and not reduce the aperture ratio , The effect of reducing the off-state current

Active Publication Date: 2014-11-26
BOE TECH GRP CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Embodiments of the present invention provide a method for manufacturing an array substrate, an array substrate, and a display device, which are used to solve the problems of high processing cost, long processing time, and easy occurrence of doping structure shift in existing technologies for manufacturing thin film transistor devices

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  • Array substrate manufacturing method, array substrate and display device
  • Array substrate manufacturing method, array substrate and display device
  • Array substrate manufacturing method, array substrate and display device

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Embodiment Construction

[0048] In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

[0049] like figure 1 As shown, the embodiment of the present invention provides a method for manufacturing an array substrate, including the following steps S11-S15:

[0050] S11, such as figure 2 and image 3 As shown, a first polysilicon island 301 and a second polysilicon island 302 are formed on the substrate 20 , and one end of the first polysilicon island 301 is vertically connected to one end of the second polysilicon island 302 .

[0051] Specifically, step S11 can be specifically implemented as the following steps A1-A3:

[0052] A1, such as figure 2 As shown, the buffer layer 25 is formed on the substrate 20 by methods such as deposition and coating.

[0053] Wherein, the substrate 20 can be a glass substrate or a quar...

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Abstract

Provided are an array substrate, a manufacturing method therefor and a display device. The array substrate comprises: a substrate; a first active layer and a second active layer, wherein one end of the first active layer is connected to one end of the second active layer; a gate electrode and gate lines, which are respectively arranged above the first active layer and the second active layer, wherein the region of the first active layer which is not covered by the gate electrode and the region of the second active layer which is not covered by the gate lines form a doping region as an ohmic contact region; a drain electrode which is arranged above the first active layer; data lines and a source electrode which are arranged above the second active layer; and a pixel electrode which is arranged in a region crosswise surrounded by the gate lines and the data lines.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a manufacturing method of an array substrate, an array substrate and a display device. Background technique [0002] In the prior art, when making some thin film transistor devices in the pixel area of ​​TFT-LCD (Thin Film Transistor LCD, thin film field effect transistor liquid crystal display), in order to reduce the off-state current Ioff, a multi-gate structure or a doped structure can be used, because the multi-gate The pole structure will reduce the pixel aperture ratio, so thin-film transistors with doped structures are often used. [0003] In the prior art, when making thin-film transistor devices in the pixel part, it is necessary to use an additional mask to make a photoresist pattern layer. In the photolithography process, it is easy to cause the doping structure to shift due to alignment errors during exposure. And because an additional mask is required, the...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/77H01L27/12G02F1/1362G02F1/1368
CPCG02F1/1368H01L29/78696G02F2001/13685H01L29/78645G02F1/13685
Inventor 张元波
Owner BOE TECH GRP CO LTD