Method for selectively etching and preparing full-isolation mixed crystal orientation SOI (silicon-on-insulator)

Abstract

The invention discloses a method for selectively etching and preparing a full-isolation mixed crystal orientation crystal orientation SOI (silicon-on-insulator) and a preparation method of a CMOS (complementary metal-oxide-semiconductor transistor) integrated circuit based on the method. The preparation method provided by the invention comprises the steps as follows: an SiGe layer is used as a virtual substrate layer of the first crystal orientation extension so as to form top strain silicon of the first crystal orientation; Si for directly extending to cover the surface of a first hard mask from a window is used as a support of connecting the top strain silicon of the first crystal orientation inside the window and the top silicon outside the window, so as to remove the SiGe layer below the top strain silicon of the first crystal orientation, and an insulated material is filled to form an insulated buried layer. Strain relaxation when the top silicon has strain also can be prevented; the top silicon formed by the method and the insulated buried layer are uniform and controllable in thickness; the strain silicon formed inside the window and the top silicon outside the window have different crystal orientations, and can respectively provide high migration rate for an NMOS (negative channel metal oxide semiconductor) and a PMOS (positive channel metal oxide semiconductor), so that the performance of the CMOS integrated circuit is improved.

Description

technical field [0001] The invention relates to a method for preparing a semiconductor device substrate, in particular to a method for preparing a fully isolated mixed crystal orientation SOI by using a selective etching technology, and belongs to the field of semiconductor device manufacturing. Background technique [0002] A complementary metal oxide semiconductor (CMOS, Complementary Metal Oxide Semiconductor) device is a semiconductor device that integrates an N-channel metal oxide semiconductor transistor (NMOS) and a P-channel metal oxide semiconductor transistor (PMOS) on the same substrate. With the continuous development of CMOS technology, how to control device stability and improve device performance has become an increasingly serious challenge faced by the continuous reduction of device size. SOI (Silicon On Insulator) refers to silicon-on-insulator technology. Because SOI technology reduces the parasitic capacitance of source and drain, the speed of SOI circuit ...

AI Technical Summary

Problems solved by technology

The disadvantage is that the PMOS device fabricated on the epitaxial layer does not have a buried oxide layer to isolate it from the substrate, so the device performance is still affected

The patent document of US Patent No. US2007 / 0281446A1 discloses a method for fabricating a mixed-oriented SOI substrate. The underlying silicon is exposed by etching trenches, and the original (100) top layer is epitaxially grown from the underlying silicon by a lateral epitaxy selective process. (110) silicon materials with different crystal orientations of silicon, so as to obtain SOI substrates with mixed crystal orientations.

However, as the feature size of devices is further reduced, the low hole mobility of common silicon materials will become one of the bottlenecks in improving device performance.

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