Non-volatile memory, memory controller and access method thereof
A non-volatile, memory technology, used in static memory, read-only memory, information storage, etc., to solve problems such as low speed
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no. 1 example
[0042] figure 1 is a schematic diagram showing the configuration of the nonvolatile memory 10 as the first embodiment of the present disclosure.
[0043] The nonvolatile memory 10 practiced as the first embodiment of the present disclosure has: an NVRAM 20 as a nonvolatile memory (NVM) cell device including an NVRAM cell array that can be randomly accessed in word units; NVRAM controller 30 of the controller.
[0044] The nonvolatile memory 10 is configured to include a host device (CPU) 40 capable of accessing the NVRAM 20 via the NVRAM controller 30 , and a DRAM 50 serving as a work memory directly accessible from the host device 40 .
[0045] [Characteristic structure and function of this embodiment]
[0046] The nonvolatile memory 10 of this embodiment is characterized in that, for accessing the nonvolatile storage area of the NVRAM 20, a first access mode allowing XIP with (ready) ECC processing and a second access mode allowing sequential ECC processing are provided....
no. 2 example
[0116] Figure 5 is a schematic diagram showing the configuration of a nonvolatile memory 10A as the second embodiment of the present disclosure.
[0117] The main differences between the nonvolatile memory 10A of the second embodiment and the nonvolatile memory 10 of the first embodiment are as follows:
[0118] The nonvolatile memory 10A is arranged such that its NVRAM 20A is equipped with the functionality of an NVRAM controller.
[0119] In conjunction with this feature, the NVRAM 20 includes a CPU interface 26, and a second ECC processing section 27 and a second buffer 28 required in the second access mode.
[0120] The NVRAM interface, not shown, does not use the handshake signal in the first access mode, and controls the handshake signal in the second access mode.
[0121] The structures and functions of the second ECC processing section 27 and the second buffer 28 are basically the same as those of figure 1 The shown second ECC processing section 33 and the second b...
no. 3 example
[0125] Figure 6 is a schematic diagram showing the configuration of a nonvolatile memory 10B as a third embodiment of the present disclosure.
[0126] The main differences between the nonvolatile memory 10B of the third embodiment and the nonvolatile memory 10A of the second embodiment are as follows:
[0127] The nonvolatile memory 10B has an NVRAM 20B including a plurality (n) of NVRAM cell arrays 21, a plurality (n) of first ECC processing sections 22, a plurality (n) of first buffers 23, a plurality of (n) first access paths 24 and a plurality (n) of second access paths 25 .
[0128] The first and second buffers are used on a shared basis. The plurality of first buffers 23-1 to 23-n also have a second buffer capability.
[0129] In the third embodiment, the plurality of NVRAM cell arrays 21-1 to 21-n connected to the first buffers 23-1 to 23-n are controlled simultaneously and in parallel.
[0130] The NVRAM interface does not use the handshake signal in the first acc...
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