Address translation method of flash FTL (Flash Translation Layer)

An address translation and flash memory technology, applied in the field of data storage and NAND flash memory, can solve the problems of slow FTL address translation speed and complicated operation, and achieve the effect of improving FTL address translation speed, less hardware resources, and improving address translation speed.

Inactive Publication Date: 2012-12-12
常州新超电子科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] The purpose of the present invention is to provide another address conversion method for flash memory FTL, aiming to solve the above-mentioned defects of the prior art, especially to solve the shortcomings of the current FTL address conversion speed and complex operation

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  • Address translation method of flash FTL (Flash Translation Layer)
  • Address translation method of flash FTL (Flash Translation Layer)
  • Address translation method of flash FTL (Flash Translation Layer)

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Embodiment Construction

[0027] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0028] The present invention takes a U disk with a capacity of 32GB as an example, uses 4 logical units (LUN) to construct a NAND Flash array, selects 4 devices (device), and each device contains a form of a logical unit to form a storage array.

[0029] In order to speed up data transmission, the present invention organizes four logical units (LUN1-LUN4) together to form a super block (Super Block, SB for short). Each logical unit contains two layers (Plane), and each layer has 2048 blocks. The present invention binds blocks with the same number in 8 layers in total of 4 logic units together to form a super block, and the super block has the same number. Since the capacity of each super block is 16MB, then for a U disk with a capacity of 32GB, the present invention can obtain 2048 super blocks altogether, and each super block contains 8 ph...

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Abstract

The invention discloses an address translation method of a flash FTL (Flash Translation Layer). The address translation method comprises the following steps of: acquiring a corresponding logic block number and a logic cluster number in the block according a logic address; searching a mapping table from logic block address spaces to super block groups according to the logic block number to obtain a corresponding physical block number and physical page number; and searching a mapping table from logic clusters to physical pages according to the physical block number and the logic cluster number in the block to obtain a corresponding physical address. According to the address translation method, addresses of physical pages corresponding to all logic clusters in the logic block can be found by only recording the physical block number and the physical page number mapped by each logic block for the final time for each logic block. Thus, the address translation speed of the FTL can be obviously increased, less hardware resource is occupied, and the address translation method has extremely high execution efficiency for reading and writing of continuous data and random data and has high flexibility.

Description

technical field [0001] The invention relates to the technical fields of data storage and NAND flash memory, in particular to an address translation method of a flash memory FTL (flash translation layer). Background technique [0002] With the development of mobile communications and the popularization of portable devices, Flash memory is widely used in many fields due to its non-volatile, high density, high access speed, low power consumption, and low price. Such as commonly used portable players, digital cameras, handheld computers, mobile phones, etc. [0003] However, NAND FLASH equipment has the following characteristics in use due to the relationship between the process: 1) The erase operation unit is larger than the write operation unit. 2) Unlike traditional hard drives, data cannot be overwritten directly, but must be erased first and then written. 3) NAND FLASH storage limits the number of writes and erases. Data is not sequentially written to storage addresses, ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/02
Inventor 黄益人董春雷周毅奚谷枫
Owner 常州新超电子科技有限公司
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