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Chip-scale package

A technology of chip size packaging and packaging, which is applied in the direction of electrical components, electric solid devices, semiconductor devices, etc., and can solve the problem of poor distribution and diffusion of the build-up dielectric layer 12 and the inability of the build-up dielectric layer 12 to be evenly distributed and covered Layer 10, delamination and other problems to achieve the effect of avoiding delamination, good adhesion, and improving reliability

Active Publication Date: 2012-12-19
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in the conventional package 1, the material of the build-up dielectric layer 12 has the problem of non-wetting to the material of the cladding layer 10, resulting in the distribution and diffusion of the build-up dielectric layer 12. Poor performance, so that the build-up dielectric layer 12 cannot be evenly distributed on the cladding layer 10
[0005] In addition, the solvent in the build-up dielectric layer 12 will damage the cladding layer 10, resulting in poor adhesion between the build-up dielectric layer 12 and the cladding layer 10, and thus delamination will occur. , resulting in poor product reliability

Method used

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Examples

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no. 1 example

[0064] see figure 2 , which is a chip-scale package 2 of the present invention, which includes: a cladding layer 20 having opposite first surfaces 20a and second surfaces 20b, embedded in the first surface 20a of the cladding layer 20 and exposed At least one chip 21 on the first surface 20a of the cladding layer 20, a buffer dielectric layer (Buffer Dielectric Layer) 22 formed on the first surface 20a of the cladding layer 20 and the chip 21, and the The wiring layer 23 on the buffer dielectric layer 22 .

[0065] The material of the cladding layer 20 is encapsulation colloid or soft material, and in this embodiment, the soft material is Ajinomoto Build-up Film (ABF), Bismaleimide-Triacine (BT), polyimide ( Polyimide, PI), silicone resin (polymerized siloxanes, silicone) or epoxy resin.

[0066] The chip 21 has an opposite active surface 21a and a non-active surface 21b, and has a plurality of electrode pads 210 on the active surface 21a of the chip 21, and the chip 21 is ...

no. 2 example

[0077] see image 3 , the difference between this embodiment and the first embodiment lies in the related design of the newly added substrate 30 , and the structures and materials of other related packages are the same, so details are not repeated here.

[0078] The package 3 is combined with a substrate 30 on the second surface 20 b of the cladding layer 20 and the non-active surface 21 b of the chip 21 .

[0079] The substrate 30 has an upper surface 30a and a lower surface 30b, the upper and lower surfaces 30a, 30b are respectively provided with circuits 31, 32 electrically connected to each other, and the upper surface 30a is bonded to the first layer of the cladding layer 20. On the two surfaces 20b and the non-active surface 21b of the chip 21, the circuit 31 of the upper surface 30a is embedded in the cladding layer 20, and the circuit 31 of the upper surface 30a has a plurality of conductive components 33, with electrical properties The conductive blind hole 230 ′ of ...

no. 3 example

[0085] see Figure 4 and Figure 4 ', the difference between this embodiment and the first embodiment lies in the related design of the newly added conductive bumps 40, 40', and the structures and materials of other related packages are the same, so no more details are given here.

[0086] The packages 4, 4' form conductive bumps 40, 40' in the cladding layer 20, and the upper ends of the conductive bumps 40, 40' are combined with the buffer dielectric layer 22 and the lower ends are exposed to the cladding. The second surface 20b, 20b' of the layer 20, 20' is used to combine the conductive component (for example: metal wire, solder, solder ball) 46, and the circuit layer 23 is electrically connected to the conductive bump 40 through the conductive blind hole 230' , 40' upper end.

[0087] In this embodiment, the conductive bumps 40, 40' are made of copper.

[0088] In addition, a metal layer 41 can be formed on the lower surface of the conductive bump 40 to combine with th...

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Abstract

A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer.

Description

technical field [0001] The present invention relates to a semiconductor package, especially a chip scale package (CSP) package. Background technique [0002] With the evolution of semiconductor technology, different packaging product types have been developed for semiconductor products. In order to pursue thinner, thinner and smaller semiconductor packages, a chip scale package (CSP) has been developed, which is characterized in that Chip-scale packages are only comparable or slightly larger than the chip size. [0003] Such as figure 1 As shown, the existing chip size package 1 includes: a hard board 17, such as a silicon substrate; a cladding layer 10 having opposite first surfaces 10a and second surfaces 10b, and the second surface 10b is arranged on the On the hard board 17, the material of the cladding layer 10 is a soft material, such as composite insulating material (Ajinomoto Build-up Film, ABF), composite resin (Bismaleimide-Triacine, BT); at least one chip 11, wh...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/29
CPCH01L23/31H01L24/19H01L23/29H01L23/3114H01L23/5389H01L23/3128H01L2224/0401H01L2224/04105H01L2224/12105H01L2224/32225H01L2224/73267H01L2924/18162
Inventor 张江城刘鸿汶许习彰廖信一邱世冠
Owner SILICONWARE PRECISION IND CO LTD
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