Grid voltage bootstrapped switch circuit

Abstract

The invention provides a grid voltage bootstrapped switch circuit. The grid voltage bootstrapped switch circuit comprises a grid voltage bootstrapped loop circuit (10) and an NMOS (N-Metal Oxide Semiconductor) switching tube (MN6), wherein the grid voltage bootstrapped loop circuit (10) is used for generating grid control voltage under the control of a clock signal, and the grid control voltage can be influenced by an input analog signal; and a grid end of the NMOS switching tube (MN6) is connected with the grid voltage bootstrapped circuit (10), a leakage end of the NMOS switching tube (MN6) is connected to an analog signal input end, a source end of the NMOS switching tube (MN6) is connected to a discrete signal output end, and the NMOS switching tube (MN6) is used for keeping the grid source voltage difference unchanged under the control of the grid control voltage, sampling the analog signal input by the analog signal input end into a discrete signal and outputting the discrete signal from the discrete signal output end. According to the grid voltage bootstrapped switch circuit provided by the invention, the nonlinearity of switching on a resistor by a switch is removed to the maximum, the signal distortion is reduced, and the circuit accuracy is increased.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a gate voltage bootstrap switch circuit realized by a CMOS process. Background technique [0002] With the development of technology, high-speed and high-precision has become the design goal of the analog-to-digital converter, and the sample-and-hold circuit is the core part of the analog-to-digital converter, and its performance determines the performance of the entire analog-to-digital converter. Therefore, it is particularly important to design a high-speed and high-precision sample-and-hold circuit. The most critical in the sample and hold circuit is undoubtedly the sampling switch. [0003] In CMOS technology, traditional sampling switches such as figure 1 As shown, it is an NMOS transistor MN, and the source 1 of the NMOS transistor is the analog signal input terminal V in , the drain 2 of the NMOS transistor is the discrete signal output terminal V out , an...

AI Technical Summary

Problems solved by technology

[0010] However, considering that when the CK signal becomes low and the CKB signal becomes high, the MP2 transistor is turned on, and the fourth node 4 is charged to a high level, and the charging charge comes from the stored charge of the capacitor C1, which is very unfavorable for the voltage of the capacitor C1 hold, which has a great influence on the sampling accuracy of the circuit

In addition, in the gate charge charging and discharging circuit 30 of the NMOS switch tube 20, the fast charging path includes MN8 and MN3, and the path resistance is relatively large, which seriously limits the charging speed.

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