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A failure address processing method and device

A technology of failure address and processing method, which is applied in the computer field, can solve problems such as waste of memory storage resources, achieve the effect of improving utilization rate and avoiding reading and writing errors

Active Publication Date: 2015-12-09
XFUSION DIGITAL TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of realizing the above information storage, the inventor found at least the following problems in the prior art: the memory storage resources are wasted due to the indiscriminate shielding of the recorded failure addresses after the system is restarted

Method used

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  • A failure address processing method and device
  • A failure address processing method and device
  • A failure address processing method and device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0055] Embodiments of the present invention provide a failure address processing method, which is applied to the startup phase of the Basic Input Output System (BIOS), such as figure 1 As shown, the method may include:

[0056] 101. Read a failure address of a failed storage unit in the first memory stored in the second memory.

[0057] Wherein, after the computer system is reset, the BIOS starts to run first. The BIOS reads the failed address of the failed storage unit in the first memory stored in the second memory, and performs a read / write test and address matching on it. The failure address is stored by an operating system (Operating System, OS) after detecting a failed unit during operation.

[0058] 102. When it is judged that the failure type of the failed storage unit corresponding to the failure address is hard failure and the allocation type of the failure address is dynamic allocation, mask the failure address.

[0059] Wherein, after the BIOS reads from the sec...

Embodiment 2

[0064] Embodiments of the present invention provide a failure address processing method, such as figure 2 As shown, the method may include:

[0065] 201. When accessing the first memory fails, store the failure address where the failure occurs in the second memory; wherein the failure includes a soft failure and a hard failure.

[0066] Wherein, the first memory includes DRAM, and the second memory includes EEPROM or flash. Memory is one of the components of a computer system and is mainly used to store instructions and data required for the processor to run. In order to facilitate the replacement, it is often made into a memory stick containing multiple DRAM chips. In addition to the DRAM chip, there is also a small-capacity EEPROM chip on the memory stick. The EEPROM chip can be accessed through the I2C bus. Information such as the number of address lines of the DRAM chip, the width of the data lines, and timing parameters are stored in the EEPROM chip. The specific forma...

Embodiment 3

[0094] An embodiment of the present invention provides a failure address processing device, which is applied to the BIOS startup phase, such as image 3 As shown, it includes: a reading unit 31 and a shielding unit 32 .

[0095] The reading unit 31 is used to read the failure address of the failed storage unit in the first memory stored in the second memory; wherein, the failure address is detected by the operating system OS after the failed unit is detected during operation. stored, the second memory is a non-volatile memory.

[0096] The shielding unit 32 is used to shield the failure when the failure type of the failure storage unit corresponding to the failure address read by the reading unit 31 is hard failure, and the allocation type of the failure address is dynamic allocation. address.

[0097] Further, such as Figure 4 As shown, the failure address processing device may further include: a first judging unit 33 and a second judging unit 34 .

[0098] The first jud...

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Abstract

The embodiment of the invention provides a fail address processing method and a fail address processing device and relates to the field of computers, and the method and the device can be used for ensuring correct memory read and write and effectively improving the utilization ratio of memory resources. The specific scheme is as follows: reading a fail address of a failed storage unit in a first storage, wherein the fail address is stored in a second storage and is stored after an OS (Operating System) detects the failed unit during the operation process, and the second storage is a nonvolatile storage; and when determining that the failure type of the failed storage unit corresponding to the fail address is hard failure and the distribution type of the fail address is dynamic allocation, shielding the fail address. The method and the device are mainly used in the fail address treating process during the starting phase of a BIOS (Basic Input / Output System).

Description

technical field [0001] The invention relates to the field of computers, in particular to a method and device for processing failure addresses. Background technique [0002] A computer system generally consists of five parts: processor, memory, input device, output device, and bus. The memory is used to store the instructions and data required for the processor to run. The memory is generally realized by using a dynamic random access memory (DRAM) of a semiconductor process, and the memory is often made into a memory bar form including a plurality of DRAM chips for easy replacement. In order to improve the reliability of the memory stick, one or two error detection and correction (Error Checking and Correction, ECC) check chips are often added to the memory stick. [0003] In the prior art, when a program accesses the memory, if there is a bit error in the data in the memory, it can be detected and corrected through the ECC check code, so that the computer can continue to op...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/07
Inventor 李延松
Owner XFUSION DIGITAL TECH CO LTD
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