Chip packaging structure of a plurality of assemblies

Abstract

Disclosed herein are chip packaging structures for packaging multiple assemblies therein. In one embodiment, a chip packaging structure can include: (i) a first assembly located at a bottom layer of the chip packaging structure; (ii) at least one second assembly located above the first assembly, where the second assembly is electrically connected to the first assembly by a plurality of first protruding structures located under the second assembly; (iii) at least one third assembly located above the second assembly, where the third assembly is electrically connected to the first assembly by a plurality of second protruding structures located outside of the second assembly; and (iv) where a first portion of the third assembly and the plurality of second protruding structures form a bent structure substantially perpendicular to a second portion of the third assembly.

Description

technical field [0001] The present invention relates to semiconductor packaging, and more particularly to a chip packaging structure comprising a plurality of components. Background technique [0002] With the increasing demand for miniaturization, light weight and multi-functionalization of electronic components, the requirements for semiconductor packaging density are getting higher and higher, so as to achieve the effect of reducing the packaging volume. Therefore, the multi-chip packaging structure has become a new hot spot. However, in a multi-chip semiconductor package structure, the connection method between chips has a crucial impact on the size and performance of the semiconductor package. [0003] figure 1 Shown is a cross-sectional view of a multi-chip packaging structure in the prior art. In this implementation, the lower chip 3 and the upper chip 5 are stacked and arranged on the printed circuit board 1 . One surface of the lower chip 3 is connected to the u...

AI Technical Summary

Problems solved by technology

[0005] In view of this, the object of the present invention is to provide a multi-component chip packaging structure to solve the problem of excessive thickness of the package and the adverse impact of the package structure on chip performance in the prior art.

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