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Distributed 8x8 low-latency high-bandwidth cross-point cache queue on-chip router

A cache queue and low-latency technology, applied in the field of distributed 8X8 low-latency high-bandwidth cross-point cache queue on-chip routers, can solve problems such as unavailable transmission, and achieve the effects of reducing complexity, low latency, and improving performance

Inactive Publication Date: 2016-04-27
SHANGHAI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, a general router will have a potential real-time closed loop between the line card and the switching network. The line card needs to know when data can be sent and when it cannot be sent. This requires a handshake signal between the line card and the switching network. , which will form a closed loop

Method used

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  • Distributed 8x8 low-latency high-bandwidth cross-point cache queue on-chip router
  • Distributed 8x8 low-latency high-bandwidth cross-point cache queue on-chip router
  • Distributed 8x8 low-latency high-bandwidth cross-point cache queue on-chip router

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Experimental program
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Effect test

Embodiment 1

[0019] Such as figure 1 As shown, a distributed 8X8 low-latency high-bandwidth cross-point cache queue on-chip router includes three components: a processor label filter (1), a cluster label filter (2), and an output module (3). Its features are: the input nodes corresponding to output ports 0, 2, 4, and 6 are mounted with processor tag filters (1); the output nodes corresponding to output ports 1, 3, 5, and 7 are mounted with cluster tags Filter (2), each output port is mounted with an output module (3). When valid data is input, the processor label filter (1) at each node detects the data sent by the input port at the same time, and ignores the data when the processor label (cluster number and core number) of the data does not match itself, if Matching will enter the accepting operation, and at the same time send the output request signal to the corresponding output module, if the permission signal is received, the data will be sent directly to the output module (3), within...

Embodiment 2

[0021] This embodiment is basically the same as Embodiment 1, and the special features are as follows:

[0022] , processor tag filter (1)

[0023] Such as figure 2 : Processor tag filter (1) is designed for 2~3 stage variable pipeline. When the data is valid, the data is stored in the first-level register, and the processor label and the value in the processor label register are taken out at the same time. If they match, a match signal is generated. When the match signal is valid and the data is valid or the FIFO is not empty, an arbitration request is generated. Signal. After the matching is successful, the data enters the second register and waits for the response signal. If the response signal has arrived and the FIFO is empty before the next clock arrives, the data is directly sent to the data bus through the multiplexer and the tri-state gate. ; If not, the data enters the FIFO queue and waits for the arbitration output. When it does not pass through the FIFO, it is...

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Abstract

The invention relates to a distributed 8X8 low latency and high bandwidth intersection buffer queue on-chip router, and aims at resolving limits of real-time loop closing of a traditional router and improving performances. The distributed 8X8 low latency and high bandwidth intersection buffer queue on-chip router is mainly composed of processor tag filters, cluster tag filters and output modules, wherein the processor tag filters are mounted on input nodes corresponding to output ports 0, 2, 4 and 6, the cluster tag filters are mounted on input nodes corresponding to output ports 1, 3, 5 and 7, and one output module is mounted on each output port. The distributed 8X8 low latency and high bandwidth intersection buffer queue on-chip router is characterized by being low in latency and high in bandwidth.

Description

technical field [0001] The invention relates to a distributed 8X8 low-delay high-bandwidth cross-point cache queue on-chip router, in particular to an on-chip router involving on-chip network technology, on-chip communication technology, and on-chip routing technology. Background technique [0002] With the advent of the era of single-chip multiprocessor CMPs (Chipmultiprocessors) and system-on-chip SoC (Systemonchip), on-chip communication has become a bottleneck that limits its development. The proposal of NoC (NetworksonChip) solves this problem structurally. The core idea of ​​NoC is to map the macroscopic computer network onto a single chip. The key component of NoC is the on-chip router, and the performance of the router is directly related to the performance of the entire system. [0003] However, a general router will have a potential real-time closed loop between the line card and the switching network. The line card needs to know when data can be sent and when it ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/861H04L12/947H04L12/931
Inventor 毕卓王镇孔维利张莹徐云川
Owner SHANGHAI UNIV