Manufacture method of alignment mark protective layer

Abstract

The invention provides a manufacture method of an alignment mark protective layer. The manufacture method of the alignment mark protective layer includes the following steps: providing a semiconductor substrate in which a zero-layer mark is formed, forming a monox layer which covers the zero-layer mark, forming at least one layer of epitaxial silicon which covers the monox layer and the semiconductor substrate, wherein the epitaxial silicon layer of the zero-layer mark area is thinner than the epitaxial silicon layer of the other areas, and oxygenizing the epitaxial silicon layer until the epitaxial silicon layer of the zero-layer mark area is oxygenized completely. The manufacture method of the alignment mark protective layer improves alignment precision and alignment capacity of photoetching.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing an alignment mark protection layer in an epitaxial silicon process. Background technique [0002] The photolithography process is a key process in the manufacture of semiconductor integrated circuits, which is used to transfer the pattern on the mask plate to the surface of the wafer. However, with the continuous reduction of the feature size and the continuous improvement of the integration level of semiconductor devices, the requirements for the precision of the photolithography process are also increased. In the semiconductor manufacturing process, in order to accurately transfer the pattern on the mask to the wafer surface, the wafer must be aligned before each exposure of the photoresist. [0003] In most current epitaxial processes, the steps of using alignment marks to perform photolithographic alignment include: providing a semiconduc...

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Problems solved by technology

[0005] In the existing semiconductor manufacturing process, especially in the multilayer epitaxial process of the super junction metal oxide semiconductor field effect transistor (Supper Junction MOSFET), as the multilayer epitaxial layer grows, the steps and morphology of the zero-layer mark will gradually After the epitaxial process, the alignment of the lithography process becomes extremely difficult, which affects the alignment accuracy of the lithography, and the alignment ability of the lithography is poor.

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