Semiconductor encapsulation piece and manufacturing method thereof

Abstract

Provided are a semiconductor encapsulation piece and a manufacturing method thereof. The semiconductor encapsulation piece comprises a silicon-containing substrate which has a first line layer and a second line layer at an upper surface and a lower surface of the substrate respectively, a semiconductor assembly which is arranged on the upper surface and is electrically connected with the first line layer, an insulating material which covers the semiconductor assembly, a third line layer which is formed on the insulating material, and a conductive blind hole which is arranged in the insulating material and is electrically connected with the first and third line layers. In addition, the silicon-containing substrate has a conductive via hole which is electrically connected with the first and second line layers. The semiconductor encapsulation piece with the conductive via hole, which is manufactured by employing a panel of silicon substrate, has greater UPH compared with the traditional semiconductor encapsulation piece which employs a BT material as the substrate, and the manufacturing cost is also reduced.

Description

technical field [0001] The invention relates to a semiconductor package and its manufacturing method, in particular to a semiconductor package with reduced production cost and its manufacturing method. Background technique [0002] With the vigorous development of the electronic industry, electronic products tend to be thinner and smaller in shape, and gradually enter the research and development direction of high performance, multi-function, and high speed in terms of function. In order to meet the requirements of multi-function, various electronic components in electronic products must be integrated, and must also meet the requirements of miniaturization, so the technology of package on package (POP) has been developed. [0003] Such as figure 1 As shown, the existing stacked package structure 1 is formed by stacking at least two semiconductor packages 1a, 1b. The semiconductor package 1a includes: a package substrate 10, which is arranged on the package substrate 10 and ...

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Problems solved by technology

[0005] However, in the existing stacked packaging structure 1, the main material of the packaging substrate 10 is a polymer compound, such as BT (bismaleimide triazine) resin, which is limited by the process capability, so that the packaging substrate 10 cannot be applied to chip I / O contacts. Products with a pitch of less than 50 μm; in addition, the traditional production of this substrate requires a large-format copper foil substrate containing BT resin for production, and the circuit integration level is not high, resulting in a small number of cut-outs for the package substrate 10, so the substrate product, package structure And the unit time output (unit per hour, UPH) of the stacked packaging structure 1 is not high, so that the manufacturing cost cannot be reduced, resulting in the bottleneck of the development of packaging and stacking technology

[0006] In addition, the semiconductor chip 13 is electrically connected to the bonding pads 100 of the packaging substrate 10 by gold wires 11, so there must be a certain distance between the bonding pads 100. If the distance between the bonding pads 100 is too small, It is not conducive to the wire bonding process, and it is easy to cause the gold wire 11 to be in contact with each other and cause a short circuit

[0007] Furthermore, in order to match the distance between the bonding pads 100, the packaging substrate 10 needs to have a certain layout area, so the volume of the packaging substrate 10 cannot be reduced, resulting in the inability to meet the miniaturization requirements.

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