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2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator using a chopper voltage reference

A voltage reference and modulator technology, applied in the direction of analog conversion, code conversion, electrical components, etc.

Active Publication Date: 2013-04-24
MICROCHIP TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0009] However, requiring four steps (stages) per sample limits the sampling rate of the sigma-delta modulator and / or requires the sigma-delta modulator to operate at a much faster speed (faster timing and higher frequency operating components, resulting in increased power usage) to complete the signal conversion within the desired time frame

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  • 2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator using a chopper voltage reference
  • 2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator using a chopper voltage reference
  • 2-phase gain calibration and scaling scheme for switched capacitor sigma-delta modulator using a chopper voltage reference

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Embodiment Construction

[0027] According to various embodiments, the mismatch can be averaged by simultaneously sampling the DAC signal and the input signal in parallel on different sets of capacitors in the front-end stage of the modulator, and by using a defined algorithm to rotate the capacitors at each sample error, while achieving that while each sample can use only two stages instead of four with less power consumption (due to less stringent requirements on the bandwidth of the amplifier present in the modulator) Sigma-Delta modulator that maintains very low gain error in the ppm range.

[0028] Simultaneously sampling the DAC signal and the input signal in parallel enables a reduction from four stages to two, and the rounding algorithm ensures proper gain error cancellation after a certain number of samples via integration in the modulator loop.

[0029] In accordance with the teachings of the present invention, rotating capacitors at each sample means assigning different sets of capacitors to...

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Abstract

A sigma-delta modulator has a chopper voltage reference providing a reference signal having a clock dependent offset voltage, a single-bit or a multi-bit digital-to-analog converter (DAC); a plurality of capacitor pairs; a plurality of switches to couple any capacitor pair to an input or reference signal; and a control unit controlling sampling through said switches to perform a charge transfer in two phases wherein any capacitor pair can be selected to be assigned to the input or reference signal, wherein after a plurality of charge transfers a gain error cancellation is performed by rotating the capacitor pairs cyclically, and wherein a DAC output value and a reference offset state define switching sequences wherein each switching sequence independently rotates said capacitor pairs and wherein at least one switching sequence is selected depending on a current DAC output value and a current reference offset state.

Description

[0001] Cross References to Related Applications [0002] This application is a continuation-in-part of U.S. Patent Application Serial No. 12 / 832,599, filed July 8, 2010, asserting U.S. Patent Application Serial No. 61 / 226,049, filed July 16, 2009 rights to United States Provisional Application, the contents of which are hereby incorporated by reference in their entirety. technical field [0003] The present invention relates to analog-to-digital converters, in particular to sigma-delta modulators, and more particularly to a method for reducing the effects of mismatch capacitors in sigma-delta modulators gain error without loss in conversion time. Background technique [0004] Today, analog-to-digital converters (ADCs) are widely used in consumer electronics, industrial applications, and the like. Typically, an analog-to-digital converter includes circuitry for receiving an analog input signal and outputting a digital value proportional to the analog input signal. This di...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M3/00H03M1/06
CPCH03M3/464H03M3/422H03M3/456H03M1/0663H03M1/0665
Inventor 文森特·奎奎姆普瓦扬·约纳加布里埃莱·贝利尼
Owner MICROCHIP TECH INC
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