Semiconductor package and method of fabricating the same

Abstract

Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes a silicon-containing substrate, a photo-sensor chip disposed on the silicon-containing substrate, a plurality of conductive lines electrically connected to the silicon-containing substrate and the photo-sensor chip, an encapsulating layer encapsulating the photo-sensor chip and the conductive lines, and a colloid lens disposed on the encapsulating layer. With the photo-sensor chip stacked on the silicon-containing substrate, a circuit board may have a reduced region that is occupied by the semiconductor package.

Description

technical field [0001] The invention relates to a semiconductor stacking technology, in particular to a semiconductor package and its manufacturing method. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. In order to meet the packaging requirements of high integration and miniaturization of semiconductor packages, it is necessary to carry more semiconductor chips and electronic components on a single packaging substrate. Currently, there are various types of semiconductor packages, such as optoelectronic devices (opto electronic devices) or micro electromechanical systems (Micro Electro Mechanical Systems, MEMS). [0003] figure 1 Shown is a semiconductor package with a photosensitive chip 11, which carries a photosensitive chip 11 and an electronic component 10 on a package substrate 1 made of BT (Bismaleimide-Triazine), and the photose...

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Problems solved by technology

[0004] However, in the prior art, the photosensitive chip 11 and the electronic component 10 are arranged on the same surface of the package substrate 1, so the package substrate 1 needs to plan two active areas C and D for carrying the photosensitive chip 11 and the electronic component 10 and their combination. The use of wires 12 leads to the inability to reduce the use area W of the packaging substrate 1, so that the occupied area of ​​the semiconductor package on the circuit board cannot be reduced, so it is difficult for electronic products to meet the needs of miniaturization

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