Method for preparing active chip packaging substrate

Abstract

The invention provides a method for preparing an active chip packaging substrate. The active chip packaging substrate includes: a core board; at least one upper active chip, embedded in the core board, whose active surface faces the lower surface of the core board, and the upper active chip is an active bare chip; and at least one lower active chip The chip is embedded in the core board, its active surface faces the upper surface of the core board, and the lower active chip is an active bare chip. In the active chip packaging substrate and the method for preparing the substrate of the present invention, since the active chip is not packaged before embedding and has been thinned, the miniaturization and light weight of the packaging structure are realized, thus simplifying the production of the substrate technology, which improves production efficiency; in addition, the present invention realizes the simultaneous embedding of multiple active bare chips on both sides of the substrate, which improves the integration; at the same time, there is a large degree of freedom and space on both sides of the substrate, and sustainable multi-layer Wiring, thereby improving process quality and electrical connection reliability.

Description

technical field [0001] The invention relates to the technical field of system packaging in the microelectronics industry, in particular to a method for preparing an active chip packaging substrate. Background technique [0002] Modern portable electronic products put forward higher requirements for microelectronic packaging. With the continuous pursuit of lighter, thinner, smaller, high reliability and low power consumption, microelectronic packaging is also moving towards higher density and smaller size. Small package form development. Microelectronic packaging will develop from packaging, less packaging to no packaging, so Direct Chip Attach (DCA) technology has attracted more and more attention. Direct chip bonding technology is a packaging technology with the highest packaging efficiency. It directly bonds the chip to the printed circuit board or substrate without packaging. The advantage is that it has better electrical properties and more direct heat dissipation chann...

AI Technical Summary

Problems solved by technology

[0006] U.S. Patent No.7663249 B2 proposes a chip packaging structure and manufacturing method, such as Figure 1B As shown, in this method, the packaged chips 108 and 208 are respectively connected to two substrates by flip-chip welding technology, and a layer of dielectric layer 120 is first laminated on a substrate connected to the packaged chip 108, and then another The substrate that has been flip-chip connected to the packaged chip 208 is pressed face down to the dielectric layer 120, and then the substrates on both sides are removed, thus realizing the embedding of multiple packaged chips, but in the above-mentioned patent, the chips are flip-chip connected to the substrate Then press the dielectric layer, so when there are many bumps and the spacing is relatively small, it is possible that the dielectric layer cannot completely fill the gap between the bumps of the chip and the bumps (ie Figure 1B In B), the existence of bubbles is caused, and the chip has been packaged, so the size of the chip itself is very large, and the package structure will be relatively large, so it is difficult to reduce the size of the entire package

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