Encapsulation structure of silicon substrate pinboard

Abstract

The invention relates to an encapsulation structure of a silicon substrate pinboard and belongs to the technical field of semiconductor encapsulation. The encapsulation structure of the silicon substrate pinboard comprises a silicon substrate carrier (1), an encapsulation region (2), a front insulation layer (31), a back insulation layer (32), a front re-wiring metal layer (41), a back re-wiring metal layer (42), a front protective layer (51) and a back protective layer (52). The encapsulation region (2), the front insulation layer (31), the back insulation layer (32), the front re-wiring metal layer (41), the back re-wiring metal layer (42), the front protective layer (51) and the back protective layer (52) are arranged on the periphery of the silicon substrate carrier (1) and are respectively and sequentially arranged on the front and the back of the silicon substrate carrier (1) and the front and the back of the encapsulation region (2). A through hole (21) for filling metal is formed in the encapsulation region (2), and the front re-wiring metal layer (41) is connected with the back re-wiring metal layer (42) through metal in the through hole (21). The encapsulation structure of the silicon substrate pinboard is simple in encapsulation structure, low in encapsulation cost and high in product yield.

Description

technical field [0001] The invention relates to a package structure of a silicon-based adapter plate, which belongs to the technical field of semiconductor package. Background technique [0002] With the development of semiconductor technology, through-silicon via interconnection technology has become a common method for semiconductor packaging. Through-silicon via interconnection technology usually includes the fabrication of through-silicon vias, PECVD (plasma enhanced vapor deposition) technology to form insulating layers, and metal filling, which greatly increases the flexibility of semiconductor packaging. [0003] Through-silicon via interconnection technology has also been applied to the packaging of silicon-based interposers. The formation of through-silicon vias mainly adopts the "BOSCH" etching method, that is, the etching and passivation processes are alternately used. The "BOSCH" etching method will eventually be The ups and downs (scallop) are left on the hole ...

AI Technical Summary

Problems solved by technology

[0003] Through-silicon via interconnection technology has also been applied to the packaging of silicon-based interposers. The formation of through-silicon vias mainly adopts the "BOSCH" etching method, that is, the etching and passivation processes are alternately used. The "BOSCH" etching method will eventually be The ups and downs (scallop) are left on the hole wall, that is, the hole wall corrugation, such as figure 1 As shown, the "BOSCH" alternate etching method is not only slow, but also the corrugation of the hole wall causes incomplete coverage of the insulating layer formed by the subsequent PECVD (plasma enhanced vapor deposition)

At the same time, in the packaging process of silicon-based interposers, the CMP (chemical mechanical polishing) process is commonly used to level the surface and expose the bottom of the metal in the through hole. During this polishing process, the metal or metal ions often migrate, making the Device leakage, resulting in product failure

The above factors have led to high cost and low product yield of the existing silicon-based interposer packaging technology

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