Silicon wafer thinning fixture with through-hole electroplating copper salient points and thinning technique

Abstract

The invention discloses a silicon wafer thinning fixture with through-hole electroplating copper salient points and a thinning technique. A fixture wafer is provided with grooves capable of containing copper salient points on a thinning silicon wafer, and aligning marks used for the thinning silicon wafer and the fixture wafer are arranged on the fixture wafer. After partial electroplating hole sealing is carried out on the through hole of the silicon wafer, front side porefilling electroplating is carried out, and copper points are formed in the front side of the silicon wafer. According to the distribution of the copper points on the silicon wafer, the grooves are etched in the fixture wafer by adopting etching, corroding or machining, the silicon wafer with the electroplating copper salient points is aligned to and fixed with the fixture wafer by using the aligning marks, and thinning is carried out on the front side and the back side of the silicon wafer by adopting a mechanical grinding process or a chemico-mechanical polishing process. The silicon wafer thinning fixture with the through-hole electroplating copper salient points and the thinning technique have the advantages that stress concentration generated when the copper salient points on the silicon wafer are directly extruded in a thinning process is avoided, the problem that wafer breaking is prone to occurring when the silicon wafer with the through-hole electroplating copper salient points is thinned can be effectively avoided, and the rate of the finished product of the thinning of the silicon wafer is improved.

Description

technical field [0001] The invention relates to semiconductor manufacturing equipment and technology, in particular to a silicon wafer thinning jig with through-hole electroplated copper bumps and a thinning process method. Background technique [0002] Three-dimensional packaging is the development trend of semiconductor packaging technology. Three-dimensional packaging requires through holes to be made on silicon wafers, and metals are filled in the through holes through electroplating, deposition and other processes to achieve vertical electrical interconnection. At the same time, two or more chips need to be stacked for system-level packaging, which requires Thinning the wafer to 100μm or even below 100μm. Wafer thinning is to cut the wafer by mechanical grinding, and mechanical cutting will form a certain thickness of damage layer on the surface of the wafer. The damaged layer on the surface of the wafer can be removed by chemical mechanical polishing process. When t...

AI Technical Summary

Problems solved by technology

During the electroplating of the through-hole of the silicon wafer, it is very easy to form copper bumps at the through-holes of the silicon wafer. During the thinning process of the wafer, it is easy to cause stress concentration at the position of the bump, which in turn causes cracks and even rupture of the wafer.

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