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Merging sort structure

A sequential logic and auxiliary controller technology, applied in the direction of concurrent instruction execution, machine execution devices, etc., can solve problems such as memory occupation, achieve stable operation, maximize resources, and achieve the effects of efficiency

Inactive Publication Date: 2013-07-31
江苏复芯物联网科技有限公司
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Problems solved by technology

[0017] The above merge sorting is based on PC operation. Its algorithm is relatively simple, and it is suitable for the sorting of various queues. Merge sorting is efficient and stable, but it takes up more memory. Its time complexity is O(Nlog(N)), and its space responsibility is high. is O(N)

Method used

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Embodiment Construction

[0029] See image 3 As shown, it is a merge operation based on registers. Its hardware structure: the stored queue includes two queue registers, the two queue registers are connected to the comparator, and the two queue registers are respectively connected to the auxiliary controller. The comparator is triggered by a rising edge, and the auxiliary control The register is set with a counter that counts the dequeue or enqueue of each queue register; queue: the queue length is N: N registers D1, D2... DN, where D1 is the head of the queue, and DN is the tail of the queue; comparator: sorted data Bit n bits, using n-bit comparators, triggered by rising edges; Auxiliary controller: each queue has a flag bit FLAG, which is counted by a flag bit FLAG, initially 0, when entering the queue, the flag is increased by one, and when leaving the queue The time mark is reduced by one, and one group of queues (two) has a group flag bit BUFFFLAG, which is used to judge the input and output swi...

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Abstract

The invention relates to the field of sort algorithms, in particular to a merging sort structure. With the adoption of an FPGA (field programmable gate array) structure, operation of merging sort is achieved; maximization of a resource and the efficiency is achieved; a requirement of sorting characteristic points of a high-definition real-time picture can be fully met; and the time complexity is better than the merging sort based on PC (personal computer) operation. The merging sort structure comprises merging components, wherein the merging components comprise storage queues; the queues are connected with comparers and auxiliary controllers; and counters for counting dequeuing or enqueuing operation are arranged on the auxiliary controllers.

Description

technical field [0001] The invention relates to the field of sorting algorithms, in particular to a merge sorting structure. Background technique [0002] Sorting algorithms have been studied in detail in the field of science and technology, and there are many mature sorting algorithms. In recent years, a variety of FPGA-based sorting methods have been proposed under different applications. According to different applications, FPGA-based sorting Generally divided into two categories: network-based sorting and linear array-based sorting. [0003] Network-based sorting generally uses a two-input swap comparator for sorting. Zhang, Y. uses a fixed-size sorting network, which is divided into an input queue, a ping-pong sorting network, and an output detection module. Martinez et al. proposed a network sorting algorithm applied to block sorting and compression, using ping-pong operations to realize data cycle processing, and the sorting unit processes 128 characters. The final r...

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Application Information

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IPC IPC(8): G06F9/38
Inventor 柴志雷
Owner 江苏复芯物联网科技有限公司
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