High speed 1553 bus protocol processor

A bus protocol and processor technology, which is applied in the field of computer communication, can solve problems such as undiscovered product descriptions, and achieve the effects of time determination, efficient CPU interface, and high efficiency

Active Publication Date: 2013-08-07
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The foreign high-speed 1553 represented by the Turbo 1553 technology of the American DDC company increases the communication rate of the 1553B bus from 1Mbps to 5Mbps on the premise that the existing 1553B bus structure remains unchanged, but no detailed description of its products has been found in China.

Method used

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  • High speed 1553 bus protocol processor
  • High speed 1553 bus protocol processor
  • High speed 1553 bus protocol processor

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Embodiment Construction

[0045] The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

[0046] see figure 1 , a high-speed 1553 bus protocol processor, which mainly contains seven modules (parts):

[0047] The host interface module is respectively connected with the register file, the interrupt management unit, and the error correction and detection dual-port memory, and handles the data conversion between the host and the register and memory in the processor;

[0048] The error correction and detection dual-port memory is respectively connected with the storage management unit, the register file and the interrupt management unit; it includes two error correction and detection codec modules, one of which is responsible for the encoding and decoding of the host access memory port, and the other is responsible for the multi-protocol core Encoding and decoding of access memory por...

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Abstract

The invention discloses a high speed 1553 bus protocol processor which comprises a clock and reset management unit, a double manchester II type decoder unit, a multi-protocol processing core, a memory management unit, a file register and interrupt management unit, a host interface unit and a dual-port remedy check storage unit. The 1553 bus protocol processor provided by the invention is high in reliability, high in CPU access efficiency, low in power consumption, easy to realize, and can realize acceleration of the 1553 bus communication speed from 1Mbps to 10Mbps reliably under the premise of indistinctively improving the physical realization difficulty of the chip.

Description

technical field [0001] The invention belongs to the field of computer communication and relates to a high-speed 1553 bus protocol processor. Background technique [0002] Since the U.S. military announced MIL-STD-1553 in 1973, the 1553 bus has been continuously developed until the U.S. military announced MIL-STD-1553B notice 2 in 1986, forming a complete digital time-division command / response multiplexing Data bus protocol. At present, the 1553B bus has been widely used in military and civilian fields all over the world, and is even considered by the US military as a bus that may never disappear. [0003] In recent years, with the continuous improvement of the overall performance requirements of aerospace and weapon electronic systems, the climax of high-speed 1553 bus technology research has been set off abroad. The bus communication rate solves the problem of insufficient 1553B bus bandwidth in some system applications. The foreign high-speed 1553, represented by the Tu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/42
CPCY02B60/1228Y02B60/1235Y02D10/00
Inventor 翟宝峰王剑峰
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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