On-chip ferrite bead inductor

Abstract

A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

Description

technical field [0001] The present invention relates generally to semiconductor structures and, more particularly, to semiconductor structures including integrated passive devices (IPDs), such as ferrite bead inductors, and methods of forming the same. Background technique [0002] A major trend in semiconductor manufacturing today is the integration of 2.5D and 3DIC chip or die packages with vertically stacked chips and direct electrical connections between chips instead of other interconnect technologies such as wire bonding and chip edge interconnect. The dies in these IC chip packages may include fine (small) pitch vertical through-substrate vias (TSVs), which may be used to make direct electrical connections to adjacent stacked dies. TSVs provide higher density interconnects and shorter signal paths, creating the possibility to form die packages with smaller form factors and thin die stacks. The TSVs in the top die can be terminated on the backside of an array of micro...

AI Technical Summary

Problems solved by technology

Therefore, when mounted on a PCB, SMD ferrite beads have a relatively large form factor and consume useful real estate

SMD ferrite bead

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