Automatic testability design system and automatic testability design method for electronic design interchange format (EDIF) netlist-level circuit based on practical extraction and reporting language (Perl)

A design method and design system technology, applied in the field of automatic testability design system, can solve the problems such as inconvenient reading and modification

Active Publication Date: 2013-09-11
HARBIN INST OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the EDIF netlist is very general and suitable for software processing, but because the EDIF netlist...

Method used

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  • Automatic testability design system and automatic testability design method for electronic design interchange format (EDIF) netlist-level circuit based on practical extraction and reporting language (Perl)
  • Automatic testability design system and automatic testability design method for electronic design interchange format (EDIF) netlist-level circuit based on practical extraction and reporting language (Perl)
  • Automatic testability design system and automatic testability design method for electronic design interchange format (EDIF) netlist-level circuit based on practical extraction and reporting language (Perl)

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Experimental program
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specific Embodiment approach 1

[0046] Specific implementation mode 1. Combination figure 1 Describe this specific embodiment, the automatic testability design system based on the EDIF netlist level circuit of Perl, it comprises circuit source code parsing module 1, flip-flop modification module 2, scan chain design module 3, testability circuit generation module 4, Test verification module 5;

[0047] The circuit source code analysis module 1 is used to analyze the EDIF netlist-level description of the digital logic circuit, and obtain the information used by all flip-flops in the circuit;

[0048] The trigger modification module 2 includes a testability trigger generation module 21 and a trigger testability modification module 22;

[0049] The trigger modification module 2 is used to complete the testability modification of all triggers in the EDIF netlist description file of the circuit according to the trigger information provided by the circuit source code analysis module;

[0050] The scan chain desi...

specific Embodiment approach 2

[0055] Embodiment 2. The difference between this embodiment and the automatic testability design system based on Perl-based EDIF netlist level circuits described in Embodiment 1 is that the testability circuit generation module 4 obtains the final design for testability. The latter circuit shields all the internal information of the circuit to the outside, and only provides an interface in the form of a common hardware description language.

specific Embodiment approach 3

[0056] The specific embodiment three, the automatic testing method of the EDIF netlist level circuit based on Perl, it is realized by the following steps:

[0057] Step 1. Use the circuit source code analysis module 1 to analyze the triggers used in the circuit, and use Perl to process in the EDIF environment;

[0058] Step 2: Use the trigger modification module 2 to modify the trigger used in the circuit for testability, and use Perl to process it in the EDIF environment;

[0059] Step 3. Use Perl to perform Verilog encapsulation on the EDIF circuit after the testability modification of the flip-flop, shield the EDIF details, and then design the scan chain for the flip-flop with the testability modification in the circuit;

[0060] Step 4. Use Perl to give the final testable circuit that conforms to Verilog syntax, and after verifying that the modification is correct, use Perl to generate an automatic test file that conforms to Tel syntax, and then realize the automatic test ...

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Abstract

The invention provides an automatic testability design system and an automatic testability design method for an electronic design interchange format (EDIF) netlist-level circuit based on a practical extraction and reporting language (Perl), relates to the automatic testability design system and the automatic testability design method for the EDIF netlist-level circuit and aims at meeting the demand for automatic testability design of the EDIF netlist-level circuit. A circuit sound code analysis module is used for analyzing EDIF netlist-level description of a digital logic circuit. A trigger modification module is used for finishing testability modification of all of triggers by using an EDIF language. A Verilog encapsulation module is used for encapsulating Verilog of an EDIF netlist-level description circuit. A scan chain connecting module is used for finishing scan chain design of the EDIF netlist-level description circuit by using a Verilog language. A testability circuit generating module is used for once more Verilog encapsulation of the circuit. A test verification module is used for generating a test file and verifying the circuit adopting the testability design. The automatic testability design system and the automatic testability design method are used for the automatic testability design of the EDIF netlist-level description circuit.

Description

technical field [0001] The invention relates to an automatic testability design system and an automatic testability design method for EDIF netlist level circuits. Background technique [0002] Nowadays, with the development of semiconductor technology, integrated circuit chips (IC) have been widely used, and the reliability of integrated circuit chips has become an important issue. The method of testing ICs has become the main way to solve the reliability of ICs, but the low testability of ICs with complex functions seriously restricts the effectiveness of IC testing. The design for testability of IC can effectively improve the controllability and observability of the circuit, and greatly improve the testability of the chip, so that IC testing can be carried out effectively. [0003] The testability design of the circuit is to modify the structure of the original circuit without affecting the function of the circuit, so that the nodes in the circuit that do not have control...

Claims

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Application Information

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IPC IPC(8): G06F11/36
Inventor 俞洋陈诚彭喜元乔立岩
Owner HARBIN INST OF TECH
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