Method for manufacturing fin-type semiconductor device with gate-surrounding structure

Abstract

The invention discloses a surrounding fence structure fin-type semiconductor device manufacturing method. After a bulk substrate is used for forming a fin, a partial zone of the lower portion of the fin is exposed by multi-layer masking films and etching, a penetrating hole is formed in the lower portion of the fin in an etching mode through the exposed zone, an insulation layer is formed below the penetrating hole, and through the penetrating hole, a surrounding fence structure which can surround the fin is further formed. A fin-type semiconductor device with the surrounding fence structure manufactured on the substrate is achieved, and cost is lowered.

Description

technical field [0001] The invention relates to semiconductor device manufacturing technology, more specifically, to a method for manufacturing a fin-type semiconductor device with a gate-enclosed structure. Background technique [0002] With the high integration of semiconductor devices, the channel length of MOSFET continues to shorten, and a series of effects that can be ignored in the long channel model of MOSFET become more and more significant, and even become the dominant factor affecting the performance of the device. This phenomenon is collectively called short channel road effect. The short channel effect will deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in the signal-to-noise ratio. [0003] In order to control the short channel effect, some improvements have been made to some aspects of traditional transistor devices. For example, on the one hand, ...

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Problems solved by technology

[0006] However, the current Fin-FETs with gate-enclosed structures are all formed on SOI (Silicon On Insulator) substrates. SOI substrates include top silicon, back substrates and buried oxide layers between them. Due to the existence of buried oxide layers, It is relatively easy to manufacture a Fin-FET with a gate-enclosed structure on an SOI substrate, but it inevitably introduces large parasitic parameters, and the cost of the SOI substrate itself is relatively high, which increases the manufacturing cost

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