A method and product thereof for realizing via-hole interconnection by bottom-up filling

Abstract

The invention discloses a method for achieving through hole interconnection by filling a through hole from bottom to top. The method includes the steps that (a) a blind hole is machined in one surface of a substrate; (b) an insulating layer, a barrier layer and a seed layer are sequentially formed on the surface, provided with the blind hole, of the substrate; (c) the surface of the seed layer is coated with photoresist, the blind hole is filled and leveled up, and then exposure and development treatment is carried out so that the photoresist can only remain on the portion, at the bottom of the blind hole, of the surface of the seed layer; (d) the portion, not covered with the photoresist, of the seed layer is removed, wherein the portion, at the bottom of the blind hole, of the seed layer is not affected; (e) the residual photoresist is removed; (f) conducting materials are filled into the blind hole to achieve generation from bottom to top; (g) the surface, not provided with the blind hole, of the substrate is thinned so that a through hole can be formed, and then the process of through hole interconnection is finished. The invention further discloses a corresponding through hole interconnection structure product. By means of the method, the process of through hole electroplating can be carried out with convenient control, low cost and high efficiency, and the through hole interconnection structure product with better filling effects can be obtained.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and more specifically relates to a method for realizing through-hole interconnection through bottom-up filling and a product thereof. Background technique [0002] In the past few decades, integrated circuit technology has maintained a high-speed development following Moore's Law, the performance of chips has been greatly improved, power consumption and cost have also been greatly reduced, but the development of electronic packaging technology is relatively slow. , has gradually become one of the bottlenecks restricting the development of semiconductor technology. The traditional two-dimensional integration form has been unable to meet the increasingly higher requirements for the speed and volume of integrated circuits in consumer electronics, aerospace and other industries. Therefore, three-dimensional integration technology is receiving more and more attention. much attention an...

AI Technical Summary

Problems solved by technology

However, the production of the seed layer in this method generally requires additional process steps, such as making auxiliary wafers and temporary bonding of the auxiliary wafers; or it is necessary to pre-fill the seed layer and electroplating on the back of the wafer to be plated; therefore, there is a long process flow and high efficiency. Defects such as inferiority

Images