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Addressing and storage integrated two read one write memory controller

A storage controller and addressing technology, which is applied in the field of operation control circuit and timing control, can solve the problems of unfavorable execution instruction sequence speed, increasing the burden of microprocessor execution program instruction flow, and costing microprocessor clock pulse cycle, etc.

Inactive Publication Date: 2016-01-06
GUANGXI UNIVERSITY OF TECHNOLOGY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Memory is a must-have part of every microprocessor, whether it is the memory embedded in the microprocessor chip or the externally expanded memory connected to the microprocessor through the system bus, including the internal register set of the microprocessor, etc. It has read and write operation functions, but the function is single, that is, according to the address value of the internal address bus of the microprocessor or the address value of the external system address bus, the register or storage unit of the address is directly read and written.
The addressing process of these memories and registers is completed by the microprocessor. For other more complex addressing methods such as indirect addressing, base address plus index addressing, it also involves address calculation, address data transmission and other processes; And the data transmission between the storage units in the memory needs to be transferred through a certain register in the microprocessor to realize the data transmission between the storage units, that is, two transfer instructions are needed to complete a certain storage in the memory. The data of the unit is transferred to another storage unit; the addressing process of the memory and the register, and the process of data transmission between the storage units in the memory will take the clock pulse cycle of the microprocessor, which increases the instruction flow of the microprocessor to execute the program The burden is not conducive to improving the speed of executing instruction sequences

Method used

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  • Addressing and storage integrated two read one write memory controller
  • Addressing and storage integrated two read one write memory controller
  • Addressing and storage integrated two read one write memory controller

Examples

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Embodiment Construction

[0140] An addressing and storage integrated two-read one-write memory controller, such as image 3 As shown, the integrated two-read-one-write memory controller includes two read-one-write memory unit I, command register and address temporary storage control module II, combinational logic circuit module III, pulse distributor_1IV, data Transmission control module Ⅴ, address channel control module _1Ⅵ, command register control module Ⅶ, pulse distributor _2Ⅷ, data transmission and read arbitration control module Ⅸ and address channel control module _2Ⅹ;

[0141] The two read-one-write storage unit I, command register and address temporary storage control module II, data transmission control module V, address channel control module_1VI, command register control module VII, data transmission and read arbitration control module IX and Address channel control module_2X connection;

[0142] The command storage and address temporary storage control module II is also connected with t...

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Abstract

A two-read-out and one-read-in storage controller integrating addressing and storage comprises a two-read-out and one-read-in storage unit, a command storage and address temporary storage control module, a combinational logic circuit module, a pulse distributor_1, a data transmission control module, an address channel control module_1, a command storage control module, a pulse distributor_2, a data transmission and read arbitration control module and an address channel control module_2. The integrated storage controller is provided with a read-write port and an independent read-out port having the read operation arbitration function. A hard-wired circuit of an FPGA is applied, commands or addresses or immediate operands needing to be read in are read in from a system bus, under the control of internal temporal pulses, direct and indirect addressing of base addresses and modify addresses of the immediate operands and reading and writing of the storage unit are autonomously finished according to the command requirements, data transmission between storage units is finished, a microprocessor can read out two operands at the same time when executing operate class commands, and execution of a command sequence is accelerated.

Description

technical field [0001] The present invention relates to an addressing and storage integrated two-read-one-write storage controller, in particular to an addressing and storage integrated two-read-one-write storage controller based on FPGA parallel operation circuit hard connection operation Control circuit and its timing control. Background technique [0002] Memory is a must-have part of every microprocessor, whether it is the memory embedded in the microprocessor chip or the externally expanded memory connected to the microprocessor through the system bus, including the internal register set of the microprocessor, etc. It has read and write operation functions, but the function is single, that is, according to the address value of the internal address bus of the microprocessor or the address value of the external system address bus, the register or storage unit of the address is directly read and written. The addressing process of these memories and registers is completed ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02
Inventor 蔡启仲余玲李克俭潘绍明李静黄仕林孙培燕
Owner GUANGXI UNIVERSITY OF TECHNOLOGY
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