Shallow trench isolation structure and forming method thereof

Abstract

The invention provides a shallow trench isolation structure and a forming method thereof. The method comprises providing a substrate, wherein a shallow trench is formed in the substrate; forming a first dielectric layer in the shallow trench, wherein an upper surface of the first dielectric layer is lower than that of the substrate; and forming an oxygen-free second dielectric layer on the first dielectric layer, wherein the second dielectric layer fully fills the shallow trench. According to the shallow trench isolation structure provided in the embodiment, oxygen diffusion paths of the first dielectric layer are blocked, a phenomenon of regrowth of silicon oxide in an active region is prevented, and at the same time, phenomena of recesses formed in adjacent areas of the active region and the shallow trench isolation structure can be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing technology, in particular to a shallow trench isolation structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor technology, the feature size of semiconductor devices is getting smaller and smaller, the density of active devices per unit area of ​​semiconductor substrate is getting higher and higher, and the distance between each active device is getting smaller and smaller, thus It makes the insulation isolation between various devices become more important. [0003] Shallow trench isolation (STI) is used as an isolation structure between semiconductor active devices, Figure 1 to Figure 3 It is a schematic cross-sectional structure diagram of forming a shallow trench isolation structure in the prior art. In the prior art, methods for forming shallow trench isolation structures include: figure 1 As shown, firstly, a pad oxide l...

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Problems solved by technology

[0007] The technical problem solved by the present invention is that the shallow trench isolation structure formed in the prior art has the problems of reduced switching control capability of semiconductor devices and current leakage, which reduces the electrical performance of semiconductor devices

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