High density 3D package

Abstract

Embodiments of the present provide an integrated circuit system, which includes an interposer having a plurality of electrical conductive vias running through the interposer, one or more high-power chips mounted on a first surface of the interposer, wherein the one or more high-power chips generate at least 10 W of heat during normal operation, one or more low-power chips mounted on a second surface of the interposer, wherein the one or more low-power chips generate less than 5 W of heat during normal operation, and the first surface and the second surface are opposite and substantially parallel to each other, and an encapsulating material formed over and configured to encapsulate the one or more high-power chips and the one or more low-power chips. Since low-power chips and high-power chips are respectively mounted on front side and back side of the interposer, the footprint of the interposer and manufacturing cost associated therewith is reduced.

Description

technical field [0001] Embodiments of the present invention relate generally to integrated circuit chip packaging, and, more particularly, to three-dimensional system-in-packages with high power chips and low power chips. Background technique [0002] The size of prior art electronic devices is decreasing day by day. To reduce the size of electronic devices, the structures that package microprocessors, memory devices, and other semiconductor devices and assemble them with circuit boards must become more compact. [0003] In the packaging of integrated circuit chips, a number of assembly techniques have been developed to reduce the overall size of the integrated circuit and circuit board assembly. For example, flip-chip bonding technology is one of the assembly methods used to provide integrated circuit packaging systems with improved integration density. FIG. 1 shows a schematic cross-sectional view of a conventional flip-chip packaging structure 100 . The flip-chip struc...

AI Technical Summary

Problems solved by technology

Further, the process of making an interposer, especially a TSV-based interposer, is complex and expensive because it provides semiconductor device Vertical electrical interconnection with the underlying PCB, and in-plane electrical interconnection between horizontally arranged side-by-side semiconductor devices by using conductive connections (such as conductive connection 116a)

Existing multi-die packages not only increase the footprint of the interposer and thus impose a heavier routing burden on the package substrate, but also increase the cost due to high interposer complexity and production challenges such as bump pitch limitations. Costs associated with interposer fabrication that arise, especially when seeking to vertically combine different integrated circuits in a single package

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